- Ensure the clock is connected to the
s_axi4_aclk port.
- Ensure the active-Low
reset signal is connected to the s_axi4_aresetn port. The reset must be deactivated
to ensure the core is in working condition.
- All the registers must be accessed
with a single AXI transaction and at word boundary.
- The DTR and DRR FIFO can be accessed
using a single transaction or a burst FIXED transaction.
- The AXI4 transactions are converted in the
bus2ip_* signal transactions.
- For each SPI transaction, it is
necessary to have data beats are available in DTR FIFO. The SPI transactions are
enabled only when the SPICR register is configured, and the slave register must
be updated to select a particular slave. The SPI transactions can be observed on
SPI interface like Slave Select, SPI clock, IO0, and IO1.
- The Slave Select line must be
asserted for any SPI transaction.