UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150) - 1.4 English - Provides information about using, customizing, and simulating the DDR3 or DDR4 SDRAM, LPDDR3 SDRAM, QDR II+ SRAM, QDR-IV SRAM, or a RLDRAM 3 interface core. It also describes the core architecture and provides details on customizing and interfacing to the core. - PG150
Document ID
PG150
Release Date
2025-05-29
Version
1.4 English
Summary
Introduction
Features
IP Facts
DDR3/DDR4
Overview
Navigating Content by Design Process
Core Overview
Feature Summary
DDR3 SDRAM
DDR4 SDRAM
Licensing and Ordering
License Checkers
Product Specification
Standards
Performance
Maximum Frequencies
Efficiency and Latency Measurements
Efficiency Workloads
Idle Latency Categories
Resource Utilization
Port Descriptions
Core Architecture
Overview
Memory Controller
Native Interface
Control and Datapaths
Control Path
Data Path
Read and Write Coalescing
Reordering
Group Machines
ECC
Read-Modify-Write Flow
ECC Module
Error Address
Latency
ECC Port Descriptions
Address Parity
PHY
Overall PHY Architecture
Memory Initialization and Calibration Sequence
DQS Gate
DQS Gate Sanity Check
Write Leveling
Read DQS Deskew and Centering
Read Per-Bit Deskew
Read DBI Per-Bit Deskew
Debugging Read DQS Centering (Simple)
Read Sanity Check
Write DQS-to-DQ
Write DQS-to-DQ Per-Bit Deskew
Write DQS-to-DQ Centering
Write DQS-to-DM/DBI
Read DQS Centering (DBI)
Write Latency Calibration
Write/Read Sanity Check
Read DQS Centering (Complex)
Write DQS-to-DQ Centering (Complex)
Read Leveling Multi-Rank Adjustment
Multi-Rank Adjustments and Checks
DQS Gate Multi-Rank Adjustment
Write Latency Multi-Rank Check
Enable VT Tracking
Write Read Sanity Check (Multi-Rank Only)
Read and Write VREF Calibration
DDR4 LRDIMM Memory Initialization and Calibration Sequence
MREP Training
MRD Cycle Training
MRD Center Training
DWL Training
MWD Cycle Training
MWD Center Training
CAL_STATUS
ERROR STATUS
Save Restore
Reset Sequence
Clamshell Topology
Migration Feature
MicroBlaze MCS ECC
Memory Settings
DDR3 Register Module
DDR4 Register Module
Designing with the Core
Clocking
Requirements
GCIO
MMCM
Input Clock Requirement
BUFGs and Clock Roots
TXPLL
Sharing of Input Clock Source (sys_clk_p)
TXPLL Usage
Additional Clocks
Reduce System Noise During Calibration
Resets
PCB Guidelines for DDR3
PCB Guidelines for DDR4
Pin and Bank Rules
DDR3 Pin Rules
Pin Swapping
DDR3 Pinout Examples
DDR4 Pin Rules
Pin Swapping
DDR4 Pinout Examples
Pin Mapping for x4 RDIMMs/LRDIMMs
Protocol Description
User Interface
app_addr[APP_ADDR_WIDTH – 1:0]
app_cmd[2:0]
app_autoprecharge
app_en
app_wdf_data[APP_DATA_WIDTH – 1:0]
app_wdf_end
app_wdf_mask[APP_MASK_WIDTH – 1:0]
app_wdf_wren
app_rdy
app_rd_data[APP_DATA_WIDTH – 1:0]
app_rd_data_end
app_rd_data_valid
app_wdf_rdy
app_ref_req
app_ref_ack
app_zq_req
app_zq_ack
ui_clk_sync_rst
ui_clk
init_calib_complete
Command Path
Write Path
Read Path
Maintenance Commands
AXI4 Slave Interface
AXI4 Slave Interface Parameters
AXI Addressing
AXI4 Slave Interface Signals
AXI4 Slave Interface Transaction Examples
Arbitration in AXI Shim
Time Division Multiplexing (TDM)
Round-Robin
Read Priority (RD_PRI_REG)
Read Priority with Starve Limit (RD_PRI_REG_STARVE_LIMIT)
Write Priority (WRITE_PRIORITY, WRITE_PRIORITY_REG)
AXI4-Lite Slave Control/Status Register Interface Block
ECC Enable/Disable
Single Error and Double Error Reporting
Interrupt Generation
Fault Collection
Fault Injection
AXI4-Lite Slave Control/Status Register Interface Parameters
AXI4-Lite Slave Control/Status Register Interface Signals
AXI4-Lite Slave Control/Status Register Map
AXI4-Lite Slave Control/Status Register Map Detailed Descriptions
ECC_STATUS
ECC_EN_IRQ
ECC_ON_OFF
CE_CNT
CE_FFA[31:0]
CE_FFA[63:32]
CE_FFD[31:0]
CE_FFD[63:32]
CE_FFD[95:64]
CE_FFD[127:96]
CE_FFE
UE_FFA[31:0]
UE_FFA[63:32]
UE_FFD[31:0]
UE_FFD[63:32]
UE_FFD[95:64]
UE_FFD[127:96]
UE_FFE
FI_D0
FI_D1
FI_D2
FI_D3
FI_ECC
PHY Only Interface
PHY Interface Signals
Clocking and Reset
Command and Address
Write Data
Read Data
PHY Control
Debug
PHY Only Parameters
EXTRA_CMD_DELAY Parameter
DM_DBI Parameter
CAS Command Timing Limitations
Minimum Write CAS Command Spacing
System Considerations for CAS Command Spacing
Additive Latency
VT Tracking
Refresh and ZQ
Ping Pong PHY
Overview
Supported Configuration
Ping Pong PHY Interface
Performance
Address Map
Controller Head of Line Blocking and Look Ahead
Autoprecharge
User Refresh and ZQCS
Periodic Reads
DIMM Configurations
DDR3/DDR4 UDIMM/SODIMM
DDR3 RDIMM
DDR4 RDIMM
SLOT0_CONFIG
SLOT0_FUNC_CS
DDR4 LRDIMM
Setting Timing Options
Steps to Change RTL Parameters
Timing Improvements for 3DS Designs
Steps to Change RTL Parameters for 3DS Designs
M and D Support for Reference Input Clock Speed
Design Flow Steps
Customizing and Generating the Core
Basic Tab
AXI Options Tab
Advanced Clocking Tab
Advanced Options Tab
Migration Options Tab
DDR3/DDR4 SDRAM I/O Planning and Design Checklist Tab
User Parameters
Setting Burst Type for PHY_ONLY Designs
Setting Additive Latency for PHY_ONLY Designs
Setting Timing Parameters for DDR4 Non-Custom Memory Parts
Output Generation
I/O Planning
Constraining the Core
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Example Design
Simulating the Example Design (Designs with Standard User Interface)
Project-Based Simulation
Project-Based Simulation Flow Using Vivado Simulator
Project-Based Simulation Flow Using Questa Advanced Simulator
Project-Based Simulation Flow Using IES
Project-Based Simulation Flow Using VCS
Simulation Speed
Using AMD IP with Third-Party Synthesis Tools
CLOCK_DEDICATED_ROUTE Constraints and BUFG
Test Bench
Stimulus Pattern
Command Encoding (Command[3:0])
Address Encoding (Address[35:0]/Address[39:0])
Command Repeat (Command Repeat[7:0])
Bus Utilization
Example Patterns
Single Read Pattern
Single Write Pattern
Single Write and Read to Same Address
Multiple Writes and Reads with Same Address
Page Wrap during Writes
Simulating the Performance Traffic Generator
DDR4 Spartan UltraScale+
Overview
Navigating Content by Design Process
Core Overview
Feature Summary
DDR4 SDRAM
Licensing and Ordering
License Checkers
Product Specification
Standards
Performance
Maximum Frequencies
Efficiency and Latency Measurements
Efficiency Workloads
Idle Latency Categories
Resource Utilization
Port Descriptions
Core Architecture
Overview
Memory Controller
Native Interface
Control and Datapaths
Control Path
Read and Write Coalescing
Reordering
Group Machines
PHY
Overall PHY Architecture
Memory Initialization and Calibration Sequence
DQS Gate
DQS Gate Sanity Check
Write Leveling
Read DQS Deskew and Centering
Read Per-Bit Deskew
Read DBI Per-Bit Deskew
Debugging Read DQS Centering (Simple)
Read Sanity Check
Write DQS-to-DQ
Write DQS-to-DQ Per-Bit Deskew
Write DQS-to-DQ Centering
Write DQS-to-DM/DBI
Read DQS Centering (DBI)
Write Latency Calibration
Write/Read Sanity Check
Read DQS Centering (Complex)
Write DQS-to-DQ Centering (Complex)
Read Leveling Multi-Rank Adjustment
Multi-Rank Adjustments and Checks
DQS Gate Multi-Rank Adjustment
Write Latency Multi-Rank Check
Enable VT Tracking
Write Read Sanity Check (Multi-Rank Only)
Reset Sequence
Clamshell Topology
Migration Feature
MicroBlaze MCS ECC
Designing with the Core
Clocking
Requirements
GCIO
MMCM
Input Clock Requirement
BUFGs and Clock Roots
TXPLL
Sharing of Input Clock Source (sys_clk_p)
TXPLL Usage
Additional Clocks
Reduce System Noise During Calibration
Resets
PCB Guidelines for DDR4
Pin and Bank Rules
DDR4 Pin Rules
Pin Swapping
DDR4 Pinout Examples
Protocol Description
User Interface
app_addr[APP_ADDR_WIDTH – 1:0]
app_cmd[2:0]
app_autoprecharge
app_en
app_wdf_data[APP_DATA_WIDTH – 1:0]
app_wdf_end
app_wdf_mask[APP_MASK_WIDTH – 1:0]
app_wdf_wren
app_rdy
app_rd_data[APP_DATA_WIDTH – 1:0]
app_rd_data_end
app_rd_data_valid
app_wdf_rdy
app_ref_req
app_ref_ack
app_zq_req
app_zq_ack
ui_clk_sync_rst
ui_clk
init_calib_complete
Command Path
Write Path
Read Path
Maintenance Commands
AXI4 Slave Interface
AXI4 Slave Interface Parameters
AXI Addressing
AXI4 Slave Interface Signals
AXI4 Slave Interface Transaction Examples
Arbitration in AXI Shim
Time Division Multiplexing (TDM)
Round-Robin
Read Priority (RD_PRI_REG)
Read Priority with Starve Limit (RD_PRI_REG_STARVE_LIMIT)
Write Priority (WRITE_PRIORITY, WRITE_PRIORITY_REG)
AXI4-Lite Slave Control/Status Register Interface Block
ECC Enable/Disable
Single Error and Double Error Reporting
Interrupt Generation
Fault Collection
Fault Injection
AXI4-Lite Slave Control/Status Register Interface Parameters
AXI4-Lite Slave Control/Status Register Interface Signals
AXI4-Lite Slave Control/Status Register Map
AXI4-Lite Slave Control/Status Register Map Detailed Descriptions
ECC_STATUS
ECC_EN_IRQ
ECC_ON_OFF
CE_CNT
CE_FFA[31:0]
CE_FFA[63:32]
CE_FFD[31:0]
CE_FFD[63:32]
CE_FFD[95:64]
CE_FFD[127:96]
CE_FFE
UE_FFA[31:0]
UE_FFA[63:32]
UE_FFD[31:0]
UE_FFD[63:32]
UE_FFD[95:64]
UE_FFD[127:96]
UE_FFE
FI_D0
FI_D1
FI_D2
FI_D3
FI_ECC
PHY Only Interface
PHY Interface Signals
Clocking and Reset
Command and Address
Write Data
Read Data
PHY Control
Debug
PHY Only Parameters
EXTRA_CMD_DELAY Parameter
DM_DBI Parameter
CAS Command Timing Limitations
Minimum Write CAS Command Spacing
System Considerations for CAS Command Spacing
Additive Latency
VT Tracking
Refresh and ZQ
Performance
Address Map
Controller Head of Line Blocking and Look Ahead
Autoprecharge
User Refresh and ZQCS
Periodic Reads
Setting Timing Options
Steps to Change RTL Parameters
Timing Improvements for 3DS Designs
Steps to Change RTL Parameters for 3DS Designs
M and D Support for Reference Input Clock Speed
Design Flow Steps
Customizing and Generating the Core
Basic Tab
AXI Options Tab
Advanced Clocking Tab
Advanced Options Tab
Migration Options Tab
DDR4 SDRAM I/O Planning and Design Checklist Tab
User Parameters
Setting Burst Type for PHY_ONLY Designs
Setting Additive Latency for PHY_ONLY Designs
Setting Timing Parameters for DDR4 Non-Custom Memory Parts
Output Generation
I/O Planning
Constraining the Core
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Example Design
Simulating the Example Design (Designs with Standard User Interface)
Project-Based Simulation
Project-Based Simulation Flow Using Vivado Simulator
Project-Based Simulation Flow Using Questa Advanced Simulator
Project-Based Simulation Flow Using IES
Project-Based Simulation Flow Using VCS
Simulation Speed
Using AMD IP with Third-Party Synthesis Tools
CLOCK_DEDICATED_ROUTE Constraints and BUFG
Test Bench
Stimulus Pattern
Command Encoding (Command[3:0])
Address Encoding (Address[35:0]/Address[39:0])
Command Repeat (Command Repeat[7:0])
Bus Utilization
Example Patterns
Single Read Pattern
Single Write Pattern
Single Write and Read to Same Address
Multiple Writes and Reads with Same Address
Page Wrap during Writes
Simulating the Performance Traffic Generator
LPDDR3
Overview
Navigating Content by Design Process
Core Overview
Feature Summary
Licensing and Ordering
License Checkers
Product Specification
Standards
Performance
Resource Utilization
Port Descriptions
Core Architecture
Overview
Memory Controller
Bank Machines
Rank Machines
Column Machine
Arbitration Block
Reordering
Precharge Policy
PHY
Overall PHY Architecture
Memory Initialization and Calibration Sequence
Command Address Calibration
Write Leveling
DQS Gate
Read Leveling
Read Per-Bit Deskew
Write DQS DQ Centering
Write DQS-to-DQ Per-Bit Deskew
Write DQS-to-DQ Centering
Write DQS DM Calibration
Write Latency Calibration
Write/Read Sanity Check
Enable VT Tracking
Reset Sequence
Designing with the Core
Clocking
Requirements
GCIO
MMCM
Input Clock Requirement
BUFGs and Clock Roots
TXPLL
Sharing of Input Clock Source (sys_clk_p)
TXPLL Usage
Additional Clocks
Reduce System Noise During Calibration
Resets
PCB Guidelines for LPDDR3
Pin and Bank Rules
LPDDR3 Pin Rules
Pinout Swapping
Pinout Examples
Protocol Description
User Interface
app_addr[APP_ADDR_WIDTH – 1:0]
app_cmd[2:0]
app_en
app_hi_pri
app_wdf_data[APP_DATA_WIDTH – 1:0]
app_wdf_end
app_wdf_mask[APP_MASK_WIDTH – 1:0]
app_wdf_wren
app_rdy
app_rd_data[APP_DATA_WIDTH – 1:0]
app_rd_data_end
app_rd_data_valid
app_wdf_rdy
ui_clk_sync_rst
ui_clk
init_calib_complete
Command Path
Write Path
Read Path
Periodic Reads
M and D Support for Reference Input Clock Speed
Design Flow Steps
Customizing and Generating the Core
Basic Tab
Advanced Clocking Tab
Advanced Options Tab
LPDDR3 SDRAM I/O Planning and Design Checklist Tab
User Parameters
Output Generation
I/O Planning
Constraining the Core
Required Constraints
Device, Package, and Speed Grade Selections
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Example Design
Simulating the Example Design (Designs with Standard User Interface)
Project-Based Simulation
Project-Based Simulation Flow Using Vivado Simulator
Project-Based Simulation Flow Using Questa Advanced Simulator
Project-Based Simulation Flow Using IES
Project-Based Simulation Flow Using VCS
CLOCK_DEDICATED_ROUTE Constraints and BUFG Instantiation
Test Bench
QDR II+ SRAM
Overview
Navigating Content by Design Process
Core Overview
Feature Summary
Licensing and Ordering
License Checkers
Product Specification
Standards
Performance
Resource Utilization
Port Descriptions
Core Architecture
Overview
PHY
Overall PHY Architecture
Memory Initialization and Calibration Sequence
BISC Calibration
Memory Initialization
Read Leveling
Case 1: RL of 2
Case 2: RL of 2.5
Read Leveling Sanity Check
Address Calibration (Enabled Only for BL2)
Address Calibration Sanity Check (Enabled Only for BL2)
Write Data Centering
Write Data Sanity Check
Write Data Bitslip Calibration
Read Bitslip Calibration
Byte Writes Centering
Byte Writes Sanity Check
Byte Writes Bitslip
Read Valid Calibration
Read Valid Sanity Check
Reset Sequence
MicroBlaze MCS ECC
Designing with the Core
Clocking
Requirements
GCIO
MMCM
Input Clock Requirement
BUFGs and Clock Roots
TXPLL
Sharing of Input Clock Source (sys_clk_p)
TXPLL Usage
Additional Clocks
Reduce System Noise During Calibration
Resets
PCB Guidelines for QDR II+ SRAM
Pin and Bank Rules
QDR II+ Pin Rules
Pin Swapping
QDR II+ Pinout Examples
Protocol Description
User Interface
Interfacing with the Core through the User Interface
Memory Interface
M and D Support for Reference Input Clock Speed
Design Flow Steps
Customizing and Generating the Core
Basic Tab
Advanced Clocking Tab
Advanced Options Tab
QDR II+ SRAM I/O Planning and Design Checklist Tab
User Parameters
Output Generation
I/O Planning
Constraining the Core
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Example Design
Simulating the Example Design (Designs with Standard User Interface)
Project-Based Simulation
Project-Based Simulation Flow Using Vivado Simulator
Project-Based Simulation Flow Using Questa Advanced Simulator
Project-Based Simulation Flow Using IES
Project-Based Simulation Flow Using VCS
Simulation Speed
Using AMD IP with Third-Party Synthesis Tools
CLOCK_DEDICATED_ROUTE Constraints and BUFG Instantiation
Test Bench
QDR-IV SRAM
Overview
Navigating Content by Design Process
Core Overview
Feature Summary
Licensing and Ordering
License Checkers
Product Specification
Standards
Performance
Resource Utilization
Port Descriptions
Core Architecture
Overview
PHY
Overall PHY Architecture
Memory Initialization and Calibration Sequence
Reset Sequence
MicroBlaze MCS ECC
Designing with the Core
Clocking
Requirements
GCIO
MMCM
BUFGs and Clock Roots
TXPLL
Sharing of Input Clock Source (sys_clk_p)
TXPLL Usage
Additional Clocks
Reduce System Noise During Calibration
Resets
PCB Guidelines for QDR-IV SRAM
Pin and Bank Rules
QDR-IV Pin Rules
QDR-IV Pinout Examples
Protocol Description
Memory Interface
User Interface
Controller Features
Command Order to the Memory
Bank Collision
Channel Wise Command Order to the Memory
Examples
Command Table
Support for Mixed Command Assertion in Per User Clock
Taking Care of Bank Access Collision of PORT A and PORT B
Command Sequence
Order of Command Processing
Interfacing with the Core through the User Interface
Physical Interface
M and D Support for Reference Input Clock Speed
Design Flow Steps
Customizing and Generating the Core
Basic Tab
Advanced Clocking Tab
Advanced Options Tab
QDR-IV SRAM I/O Planning and Design Checklist Tab
User Parameters
Output Generation
I/O Planning
Constraining the Core
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Example Design
Simulating the Example Design (Designs with Standard User Interface)
Project-Based Simulation
Project-Based Simulation Flow Using Vivado Simulator
Project-Based Simulation Flow Using Questa Advanced Simulator
Project-Based Simulation Flow Using IES
Project-Based Simulation Flow Using VCS
Simulation Speed
Using AMD IP with Third-Party Synthesis Tools
CLOCK_DEDICATED_ROUTE Constraints and BUFG Instantiation
Test Bench
RLDRAM 3
Overview
Navigating Content by Design Process
Core Overview
Feature Summary
Licensing and Ordering
License Checkers
Product Specification
Standards
Performance
Maximum Frequencies
Resource Utilization
Port Descriptions
Core Architecture
Overview
Memory Controller
PHY
Overall PHY Architecture
Memory Initialization and Calibration Sequence
Read Clock Alignment
Read DQ Deskew
Read DQ Training (Simple)
Read QVLD Training
Write DQ/DM Deskew
Write/Read Sanity Check Post Write DQ/DM Deskew
Byte Slip Training
QVLD Slip Training
Write/Read Sanity Check Post Byte/QVLD Slip Training
QVLD Align Training/Byte Align Training
Write/Read Sanity Check Post QVLD/Byte Align Training
Read DQ Training (Complex)
Final Write/Read Sanity Check
Reset Sequence
MicroBlaze MCS ECC
Designing with the Core
Clocking
Requirements
GCIO
MMCM
Input Clock Requirement
BUFGs and Clock Roots
TXPLL
Sharing of Input Clock Source (sys_clk_p)
TXPLL Usage
Additional Clocks
Resets
PCB Guidelines for RLDRAM 3
Pin and Bank Rules
RLDRAM 3 Pin Rules
Pin Swapping
RLDRAM 3 Pinout Examples
Protocol Description
Memory Interface
User Interface
Command Request Signals
Interfacing with the Core Through the User Interface
User Address Bit Allocation Based on RLDRAM 3 Configuration
Physical Interface
M and D Support for Reference Input Clock Speed
Design Flow Steps
Customizing and Generating the Core
Basic Tab
Advanced Clocking Tab
Advanced Options Tab
RLDRAM 3 SDRAM I/O Planning and Design Checklist Tab
User Parameters
Setting TWTR Check Parameter OFF for RLDRAM 3 Designs
Output Generation
I/O Planning
Constraining the Core
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Example Design
Simulating the Example Design (Designs with Standard User Interface)
Project-Based Simulation
Project-Based Simulation Flow Using Vivado Simulator
Project-Based Simulation Flow Using Questa Advanced Simulator
Project-Based Simulation Flow Using IES
Project-Based Simulation Flow Using VCS
Simulation Speed
Using AMD IP with Third-Party Synthesis Tools
CLOCK_DEDICATED_ROUTE Constraints and BUFG
Test Bench
Traffic Generator
Overview
Simple Traffic Generator
Advanced Traffic Generator
Traffic Generator Default Behavior
Traffic Generator Description
Feature Support
Usage
Using VIO to Control ATG
Traffic Error Detection
How to Program Traffic Generator Instruction
Traffic Generator Structure
Traffic Generator Supported Interface and Configuration
How to Program Victim Mode/Victim Select/Victim Aggressor Delay
How to Program PRBS Data Seed
How to Program Linear Data Seed
How to Program Linear Address Seed
Read/Write Submode
QDR II+ and QDR-IV SRAMs ATG Support
Multiple IP Cores
Overview
Creating a Design with Multiple IP Cores
Sharing of a Bank
Sharing of Input Clock Source
XSDB and dbg_clk Changes
MMCM Constraints
Debugging
Overview
Finding Help with AMD Adaptive Computing Solutions
Documentation
Solution Centers
Answer Records
Technical Support
Debug Tools
XSDB Debug
Memory IP Debug GUI Usage
Memory IP Debug Tcl Usage
Example Design
Debug Signals
Vivado Design Suite Debug Feature
Reference Boards
Hardware Debug
Memory IP Usage
General Checks
Debugging DDR3/DDR4 Designs
Calibration Stages
Memory Initialization
Debug Signals
Determine the Failing Calibration Stage
Manually Analyzing the XSDB Output
Understanding Calibration Warnings (Cal_warning)
Debugging DQS Gate Calibration Failures
Debug
Expected Results
Hardware Measurements
Debugging Write Leveling Calibration Failures
Debug
Expected Results
Hardware Measurements
Read Leveling Calibration Overview
Debugging Read Per-Bit Deskew Failures
Debug
Expected Results
Hardware Measurements
Debugging Read Per-Bit DBI Deskew Failures
Debug
Expected Results
Hardware Measurements
Debugging Read DQS Centering (Simple/MPR) Failures
Debug
Expected Results
Hardware Measurements
Write Calibration Overview
Debugging Write Per-Bit Deskew Failures
Debug
Hardware Measurements
Expected Results
Debugging Write DQS Centering Failures
Debug
Hardware Measurements
Expected Results
Write Data Mask Calibration
Write DQS-to-DM Per-Bit Deskew
Write DQS-to-DM Centering
Debug
Hardware Measurements
Expected Results
Debugging Read DQS Centering with DBI
Debug
Expected Results
Hardware Measurements
Write Latency Calibration
Debug
Hardware Measurements
Expected Results
Debugging Read Complex Pattern Calibration Failures
Debug
Expected Results
Hardware Measurements
Debugging Write Complex Pattern Calibration Failures
Calibration Overview
Debug
Expected Results
Hardware Measurements
Multi-Rank Adjustments and Checks (Multi-Rank Designs Only)
Calibration Overview
Common Read Leveling Settings
DQS Gate Adjustment
Write Latency Check between Ranks
Debug
Expected Results
Hardware Measurements
Debugging Write and Read Sanity Checks
Calibration Overview
Debug
Hardware Measurements
VT Tracking
Tracking Overview
DQS Gate Tracking
Debug
Expected Results
BISC VT Tracking
Debug
Expected Results
Calibration Times
Debugging Data Errors
General Checks
Replicating Data Errors Using the Advanced Traffic Generator
ATG Setup
ATG Debug Programming
ATG Debug Read/Write Error/First Error Bit/First Error Address
ATG Debug First Error Bit/First Error Address/Sticky Error Bit
ATG Debug WatchDog Hang
Isolating the Data Error
Determining If a Data Error is Due to the Write or Read
Analyzing Read and Write Margin
Analyzing Calibration Results
Determining Window Size in ps
Conclusion
Upgrading
XCKU095/XCVU095 Recommended Memory Pinout Configurations
Introduction
Memory Interface Pin Placement
XCKU095 FFVA1156 Package
XCKU095 and XCVU095 in FFVC1517 Package
XCKU095 and XCVU095 in FFVB1760 Package
XCVU095 FFVA2104 Package
XCKU095 and XCVU095 in FFVB2104 Package
Additional Recommendations
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices