Systolic Multiply-Accumulate - 7.2 English - PG149

FIR Compiler LogiCORE IP Product Guide ( PG149)

Document ID
PG149
Release Date
2025-06-11
Version
7.2 English

The following figure shows the Systolic Multiply-Accumulate architecture implementing a pipelined Direct-Form filter.

Figure 1. Pipelined Direct - Form

The following figure shows a multi-MAC implementation for this architecture.

Figure 2. Systolic Multi - MAC Implementation

The architecture is directly supported by the DSP Slice and results in area-efficient and high performance filter implementations. The structure also extends to exploit coefficient symmetry, thus providing further resource savings.