Super Sample Rate - 7.2 English - PG149

FIR Compiler LogiCORE IP Product Guide ( PG149)

Document ID
PG149
Release Date
2025-06-11
Version
7.2 English

When the required sample frequency is greater than the clock frequency, the core accepts multiple parallel samples every clock cycle. The number of parallel samples is determined by calculating the ratio of between the sample frequency and clock frequency. It can also be specified using a fractional input or output sample period.

As with the sample period for non-super sample rate configurations the number of parallel outputs is increased or reduced to reflect any specified integer rate change.