The simulation debug flow for Mentor Graphics Questa Advanced Simulator is illustrated in the following figure. A similar approach can be used with other simulators.
Figure 1. Simulator Flow Diagram
Note: If you are simulating a netlist,
ensure that you allow time for the Global System Reset before applying stimulus. Refer to
the
Vivado Design Suite User Guide: Logic
Simulation (UG900) for information on the Global
System Reset.