Revision History - Revision History - 7.2 English - PG149

FIR Compiler LogiCORE IP Product Guide ( PG149)
Document ID
PG149
Release Date
2025-12-17
Version
7.2 English

The following table shows the revision history for this document.

Section Revision Summary
12/17/2025 Version 7.2
Features Updated topic.
Feature Support Matrix Updated figures and added additional description.
Resets Added reset coefficient vector details.
Fixed Fractional Rate Resampling Filters Updated topic.
Filter Coefficient Data Updated topic.
Single-Rate FIR Updated code examples.
Half-Band Filter Updated code example.
Hilbert Transform Updated code example.
Interpolated Filter Updated code example.
Super Sample Rate Filters Updated topic.
Filter Options Tab Updated parameter descriptions.
Implementation Tab Updated parameter descriptions.
Interface Tab Updated parameter descriptions.
User Parameters Updated parameters.
Vitis Model Composer Updated topic.
Interface Updated topic.
Constants Updated C model constants.
Structures Added data type entry type.
Model Configuration Functions Added data_send_complex reference.
Model Operation Functions Added new complex function.
Updating from FIR Compiler Versions 6.0 through 6.3 Added new parameters.
Updating from FIR Compiler v5.0 Added new parameters.
Parameter Changes Added new parameters.
Reference Boards Added supported Versal adaptive SoC boards.
06/11/2025 Version 7.2
Feature Support Matrix Updated for super sample rate support.
Clocking Updated the section.
CONFIG Channel Updated the section.
Super Sample Rate Filters Updated the section.
10/26/2022 Version 7.2
Answer Record Updated Answer Record
01/21/2021 Version 7.2
General Updates Added Versal support.
06/10/2020 Version 7.2
Overview
  • Updated Features.
  • Added new note to the Feature Support Matrix table.
  • Updated Notable Limitations.
Designing with the Core Updated Event Interface.
01/31/2020 Version 7.2
Designing with the Core
  • Added RELOAD descriptions to Resets and description to Event Interface.
  • Updated the Transpose Multi - MAC Implementation image.
Design Flow Steps Added note to the Hardware Oversampling Specification topic.
11/18/2015 Version 7.2
General Updates
  • UltraScale+ device support added.
  • Note added to highlight channel sequence switching implication.
06/24/2015 Version 7.2
General Updates
  • TDATA for Reload Channel updated.
  • Half-band sections updated to show coefficient symmetry being exploited.
C Model NT defined for Windows in C Model.
10/01/2014 Version 7.2
General Updates
  • Added details about Super Sample Rate.
  • Updated fractional decimation content and GUI section to reflect changes to the Sample Period parameter.
04/02/2014 Version 7.1
General Update Added link to resource utilization numbers
Design Flow Steps Added table.
12/18/2013 Version 7.1
General update Added UltraScale architecture support
10/02/2013 Version 7.1
General Update Minor updates to IP Facts table and Migrating appendix
06/19/2013 Version 7.1
Designing with the Core Document changes for this release:
  • Added Input and Output Sample Rate.
  • Added Coefficient Reload section.
  • Updated GUI section to reflect core version 7.1.
  • Document revision number advanced to 7.1 to align with core version number.
03/20/2013 Version 1.0
General Update Initial release as a Product Guide; replaces DS795 and UG853. There are no other document changes for this release.