Ports - 7.2 English - PG149

FIR Compiler LogiCORE IP Product Guide ( PG149)

Document ID
PG149
Release Date
2025-06-11
Version
7.2 English

Input / Output Data Channels

ND is mapped to s_axis_data_tvalid

RFD is mapped to s_axis_data_tready

RDY is mapped to m_axis_data_tvalid

Configuration Channel

FILTER_SEL is mapped to the filter select field of the s_axis_config_tdata bus

Drive s_axis_config_tvalid with the same signal driving s_axis_data_tvalid.

Note: For decimation filters s_axis_config_tvalid must be driven at the output rate. Configuration packets are consumed at the lower output rate and if supplied at the input rate the Configuration Channel FIFO becomes full and s_axis_config_tready is deasserted and input packets ignored.

Tie s_axis_config_tlast to 0 and ignore event_s_axis_config_*.

Reload Channel

The format of the reload channel has changed such that COEF_FILTER_SEL is now pre-pended to the reload packet on the s_axis_reload_tdata bus.

COEF_DIN is mapped to s_axis_reload_tdata bus

COEF_WE is mapped to s_axis_reload_tvalid

COEF_LD is mapped to s_axis_reload_tlast but is now asserted at the end of a reload packet