- Output TREADY (Data Channel Options)
- Set to FALSE. Disables back-pressure facility and guarantees fixed latency.
- Input FIFO (Data Channel Options)
- Set to FALSE. Disables the input FIFO on the S_AXIS_DATA channel and minimizes FPGA logic resources.
- Synchronization Mode (CONFIG Channel Options)
- Set to On Vector. This ensures the filter select values is updated on every processing cycle.
- Configuration Method (CONFIG Channel Options)
- Set to By Channel when applicable. This ensures a unique filter select value can be set for every interleaved data channel.
- Reload Slots (RELOAD Channel Options)
- Set to the number of coefficient sets specified
- Data Vector Reset (Control Signals)
- Set to FALSE. Minimizes FPGA logic resources and matches FIR Compiler v5.0 reset behavior.