An interpolated FIR (IFIR) filter (see Multi-Rate Systems and Filter Banks Ref [2]) has a similar architecture to a conventional FIR filter, but with the unit delay operator replaced by k-1 units of delay. k is referred to as the zero-packing factor. The following figure shows a N-tap IFIR filter. This architecture is functionally equivalent to inserting k-1 zeros between the coefficients of a prototype filter coefficient set.
Interpolated filters are useful for realizing efficient implementations of both narrow-band and wide-band filters. A filter system based on an IFIR approach requires not only the IFIR but also an image rejection filter. References, Multi-Rate Systems and Filter Banks and XtremeDSP Design Manual [Ref 8] provide the details of how these systems are realized, and how to design the IFIR and the image rejection filters.
The IFIR filter implementation takes advantage of the k-1 zeros in the impulse response to realize an area-efficient FPGA implementation. The FPGA area required by an IFIR filter is not a strong function of the zero-packing factor.
The interpolated FIR should not be confused with an interpolation filter. Interpolated filters are single-rate systems employed to produce efficient realizations of narrow-band filters and, with some minor enhancements, wide-band filters can be accommodated. There is no inherent rate change when using an interpolated filter – the input rate is the same as the output rate.