Interface Tab - Interface Tab - 7.2 English - PG149

Data Channel Options

TLAST

tlast can either be Not Required, Vector Framing or Packet Framing. Selecting Not Required means that the core does not have the port; selecting Vector Framing means that tlast is expected to denote the last sample of an interleaved cycle of data channels; selecting Packet Framing means that the core does not interpret tlast, but passes the signal to the output DATA channel tlast with the same latency as the datapath.

Output TREADY

This field enables the m_axis_data_tready port. With this is port enabled, the core supports back-pressure. Without the port, back-pressure is not supported, but resources are saved and performance is likely to be higher.

Input FIFO

Selects a FIFO interface for the S_AXIS_DATA channel. When the FIFO has been selected data can be transferred in a continuous burst up to the size of the FIFO (default 16) or, if greater, the number of interleaved data channels. The FIFO requires additional FPGA logic resources.

TUSER Input

The input TUSER port can independently and optionally convey a User Field and/or a Chan ID Field with four options.

TUSER Output

The output TUSER port can optionally carry a User Field and/or a Chan ID Field. The presence of a User field in this port is coupled to the presence of a User Field in the TUSER input selection, because the User Field, if present, is not interpreted by the core, but conveyed from input DATA channel to Output Channel with the same latency as the datapath to ease system design.

User Field Width

Range 1 to 256 bits. This parameter is automatically set in the IP integrator but can also be overridden.

See TUSER Options for further details.

Configuration Channel Options

The CONFIG channel is used to select the active filter coefficient set. The channel is also used to apply newly reload filter coefficients. See CONFIG Channel for full details.

Synchronization Mode

On Vector

Configuration packets, when available, are consumed and their contents applied when the first sample of an interleaved data channel sequence is processed by the core. When the core is configured to process a single data channel configuration packets are consumed every processing cycle of the core.

On Packet

Further qualifies the consumption of configuration packets. Packets are only consumed after the core has received a transaction on the S_AXIS_DATA channel where s_axis_data_tlast has been asserted.

Configuration Method

Single

A single coefficient set is used to process all interleaved data channels.

By Channel

A unique coefficient set is specified for each interleaved data channel.

Reload Channel Options

Reload Slots

Range 1 to 256. Specifies the number of coefficient sets that can be loaded in advance. Reloaded coefficients are only applied to the core after a configuration packet has been consumed. See RELOAD Channel and CONFIG Channel for more details.

Control Signals

aclken

Determines if the core has the aclken pin.

aresetn

Determines if the core has the aresetn pin.

Reset Data Vector

Specifies if aresetn resets the data vector as well as the control signals. Data vector reset requires additional FPGA logic resources. When no data vector reset has been selected an additional data_valid field is present in the m_axis_data_tuser bus which can be used as further qualification of the output data of the core. See Resets and Input and Output DATA Channels for more details.

Blank Output

Specifies that the core output to be blanked (forced to zero) following a reset until the data vector is completely filled with new data. This requires minimal additional FPGA logic resources.

Reset Coefficient Vector

Specifies if aresetn resets the coefficient vector as well as the control signals. See Resets for more details.