|
Core
Specifics |
| Supported Device Family(1)
|
AMD Versal™
adaptive SoC, AMD UltraScale+™
, AMD UltraScale™
, AMD Zynq™ 7000 SoC, 7 series
|
| Supported User Interfaces |
AXI4-Stream
|
| Resources |
Performance and Resource
Utilization web page
|
| Provided with Core
|
| Design Files |
Encrypted RTL |
| Example Design |
Not Provided |
| Test Bench |
VHDL |
| Constraints File |
Not Provided |
| Simulation Model |
Encrypted VHDL |
| Supported S/W Driver |
N/A |
| Tested
Design Flows(2)
|
| Design Entry |
AMD Vivado™ Design Suite
System Generator for DSP |
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
AMD Vivado™
Synthesis |
| Support |
| Release Notes and Known
Issues |
Master Answer Record: 54502
|
| All AMD Vivado™
IP Change Logs |
Master Vivado IP Change Logs: 72775
|
|
Support web page
|
- For a complete listing of supported devices, see the
Vivado IP catalog.
- For the supported versions of
third-party tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|