For fractional rate change filters the effective sample period must be considered because most core configurations require a fractional input or output sample period.
Fractional interpolation filters (see Fixed Fractional Rate Resampling Filters) use the specified input sample period to determine the number of clock cycles available to produce the worst case number of output samples for the specified rate change. Fixed Fractional Rate Resampling Filters illustrates a 5/3 rate change filter. For every input sample, the core produces either 1 or 2 output samples in the sequence 2, 2, 1. For this example, the worst case number of output samples per input is 2. If the input sample period was specified as 4, the output sample period needs to be 3/5 * 4 = 2.4 clock cycles. The core generates one output sample per 2 clock cycles, 4 (input rate)/ 2 (worst case outputs per input). If 3 input samples are provided at the specified input rate of 4 clock cycles per sample, without halting, the core generates the 5 output samples, in the previously defined pattern, with a sample period of 2 clock cycles. This means the core has output 5 samples in 12 clock cycles, giving an effective sample period of 2.4 clock cycles. The pattern then repeats for the next 3 input samples. See in the following figure.
The core optionally supports an input FIFO on the S_AXIS_DATA input channel.
Data can be supplied at full rate until the FIFO becomes full, when the
s_axis_data_tready signal is deasserted. The core continues to
consume data at the specified input sample period. The FIFO can be used to supply input
samples at a rate that better suits the system, as long as the effective sample rate
matches that specified for the input sample rate of the core and it is not starved of
data.
If the input sample period divided by the worst case number of outputs per input
leaves a non-zero remainder the core rounds down and generates output samples at the
lower sample period. In this circumstance, it requests input samples at the higher rate,
indicated by asserting s_axis_data_tready (see AXI4-Stream Considerations for more details), but it is not
necessary to provide the input samples at this higher rate. Consider the previous
example but change the specified input sample period to 3 clock cycles giving an output
sample period of 1.8 clock cycles. The core generates one output per clock cycle, 3
(input rate)/ 2 (worst case outputs per input) round down. As a result, the core
requests input data every 2 clock cycles but the specified input sample period needs to
be maintained by the system. 3 inputs samples at 3 clock cycles per sample generates 5
output samples in 9 clock cycles, one sample per clock cycle with an idle cycle, giving
an effective output sample period of 1.8 clock cycles. See the following figure.
Fractional decimation filters (see Fixed Fractional Rate Resampling Filters) use the specified output sample period to determine the
number of clock cycles available to calculate each output sample. The output sample
period can be directly specified on the GUI or is calculated from the specified input
sampling and clock frequencies. The core generates an output sample only when enough
inputs are supplied. Fixed Fractional Rate Resampling Filters illustrates how
many input samples are required per output for a 3/5 rate change filter. The core
generates outputs at the specified sample period. The input samples can be supplied at
full rate, one per clock cycle, until the input buffer is full. As the core consumes
input samples it can accept more from the system. This results in an effective sample
rate that matches that specified on the GUI. The core controls the input rate using the
s_axis_data_tready signal.