A wide range of filter types can be implemented in an AMD Vivado™ Integrated Design Environment (IDE): single-rate, polyphase decimators and interpolators and half-band decimators and interpolators. Structure in the coefficient set is exploited to produce area-efficient FPGA implementations. Sufficient arithmetic precision is employed in the internal datapath to avoid the possibility of overflow.
The conventional single-rate FIR version of the core computes the convolution sum defined in the following equation, where N is the number of filter coefficients.
The following figure shows the conventional tapped delay line realization of this inner-product calculation, and although the figure is a useful conceptualization of the computation performed by the core, the actual FPGA realization is quite different.
One or more time-shared multiply-accumulate (MAC) functional units service the N sum-of-product calculations in the filter. The core automatically determines the minimum number of MAC engines required to meet user-specified throughput.