The Detailed Implementation Options screen is used to configure various control and implementation options.
- Filter Architecture
- Two filter architectures are supported: Systolic Multiply-Accumulate and Transpose Multiply-Accumulate.
Optimization Options
- Goal
- Specifies if the core is required to operate at maximum possible speed (Speed or Custom option) or minimum area (Area option).
Recommended: The Area option is the recommended
default and normally achieves the best speed and area for the design.
In certain configurations, the Speed or Custom setting might be required to improve performance at the expense of overall resource usage. The Speed option selects all the possible optimizations supported by the core. The Custom option enables the Select Optimization and List parameters where individual optimizations can be specified. This provides finer control over the optimizations applied to specifically target any critical paths.
- Select Optimization
- This is a helper parameter that can be used to select/deselect the entries in the Optimization List. Selecting All fully populates the list with all possible optimizations. This does the same as selecting the Speed Optimization Goal. Selecting None deselects all optimizations. Selecting a specific optimization toggles its entry in the Optimization List.
- List
- Comma delimited list that specifies which optimizations are implemented by the core.
- Data_Path_Fanout
- Adds additional pipeline registers on the data memory outputs to minimize fan-out. Useful when implementing large data width filters requiring multiple DSP slices per multiply-add unit.
- Pre-Adder_Pipeline
- Pipelines the pre-adder when implemented using fabric resources. This may occur when a large coefficient width is specified.
- Coefficient_Fanout
- Adds additional pipeline registers on the coefficient memory outputs to minimize fan-out. Useful for Parallel channels or large coefficient width filters requiring multiple DSP slices per multiply-add unit.
- Control_Path_Fanout
- Adds additional pipeline registers to control logic whenParallel channels have been specified.
- Control_Column_Fanout
- Adds additional pipeline registers to control logic when multiple DSP columns are required to implement the filter.
- Control_Broadcast_Fanout
- Adds additional pipeline registers to control logic for fully parallel (one clock cycle per channel per input sample) symmetric filter implementations.
- Control_LUT_Pipeline
- Pipelines the Look-up tables required to implement the control logic for Advanced Channel sequences.
- No_BRAM_Read_First_Mode
- Specifies that Block RAM READ-FIRST mode should not be used. This can increase the achievable FMax of the core configuration.
- Optimal_Column_Lengths
- Partitions the DSP slice columns to maximize speed when multiple DSP slice columns are required for non-symmetric filter implementations.
- Data_Path_Broadcast
- Forces the use of a fabric-efficient implementation for single rate fully parallel symmetric filter configurations. For single channel configurations, this can result in a lower FMax for filters with a large number of taps. This structure is available only in configurations with a single DSP column, single filter set, and basic interleaved channels.
- Disable_Half_Band_Center_Tap
- Disables the half-band interpolation center tap optimization. When selected, a DSP slice is used to implement the center tap. This optimization applies only to UltraScale devices.
- Other
- Miscellaneous optimizations.
Note: All optimizations maybe specified but are only implemented
when relevant to the core configuration.
Memory Options
The memory type can either be user-selected or chosen automatically to suit the best implementation options. Choosing Distributed can result in shift register implementation where appropriate to the filter structure. Inappropriate use of forcing the RAM selection to be either Block or Distributed can lead to inefficient resource usage.
Recommended: The default Automatic mode is recommended
for most implementations.
- Data Buffer Type
- Specifies the type of RAM to be used to store data within a MAC element. You can select either Block or Distributed RAM options, or select Automatic to allow the core to choose the memory type appropriately.
- Coefficient Buffer Type
- Specifies the type of RAM to be used to store coefficients within a MAC element. You can select either Block or Distributed RAM options, or select Automatic to allow the core to choose the memory type appropriately.
- Input Buffer Type
- Specifies the type of RAM to be used to implement the data input buffer, where present. You can select either Block or Distributed RAM options, or select Automatic to allow the core to choose the memory type appropriately.
- Output Buffer Type
- Specifies the type of RAM to be used to implement the data output buffer, where present. You can select either Block or Distributed RAM options, or select Automatic to allow the core to choose the memory type appropriately.
- Preference for Other Storage
- Specifies the type of RAM to be used to implement general storage in the datapath. You can select either Block or Distributed RAM options, or select Automatic to allow the core to choose the memory type appropriately. Because this covers several different types of storage, it is recommended that you specify this type of memory directly only if you really need to steer the core away from using a particular memory resource (for example, if you are short of block RAMs in your overall design).
DSP Slice Column Options
The Vivado IDE displays the number of independent DSP chains, and their length, required to build the specified filter configuration.
- Multi-column Support
- Implementations of large high speed filters might require chaining of DSP slice elements across multiple DSP columns. Where applicable (the feature is only enabled for multi-column devices), you can select the method of folding FIR Compiler v7.2 85 of the filter structure across the multiple columns, which can be Automatic (based on the selected device for the project) or Custom (you specify the length of each column). Multiple Column Filter Implementation describes the multi-column implementation in more detail.
- Device Column Lengths
- Displays the column length pattern in a comma delimited list for the selected project device.
- Available Column Lengths
- Displays the column length pattern available for a single DSP chain. The GUI reduces the Device Columns Lengths given the number of independent DSP chains required by the filter configuration. The generated column pattern considers the Optimization Goal specified.
- Column Configuration
- Specifies the individual column lengths, in a comma delimited list, that implement a single DSP chain. When Automatic has been selected, the column lengths are determined by the GUI starting with the first column in the available column pattern. When Custom is selected, you can specify the desired column pattern. The number and length of the columns cannot exceed the available column pattern and the column lengths must sum to the DSP chain length. When the available columns have various lengths, it might be desirable to skip a particular column; this can be done by specifying a zero column length, for example 10,0,22. The specified column configuration does not guarantee that the downstream tools place the columns in the desired sequence.
- Inter-column Pipe Length
- Pipeline stages are required to connect between the columns (Non-symmetric filter implementations only), with the level of pipelining required being dependent upon the required system clock rate, the chosen device, and other system-level parameters. Choice of this parameter is always left for you to specify.