The DSP slice resource usage is influenced by the data and coefficient width specified. When the data and coefficient widths are specified to be greater than the input width of the DSP slice, the core uses multiple DSP slice columns to implement the filter. The following table provides a guide to the number of DSP columns that are required for various combinations of data and coefficient widths.
| Data Width | Coefficient Width | Number of DSP Slice Columns | ||
|---|---|---|---|---|
| Unsigned | Signed | Unsigned | Signed | |
| <=24 | <=25 | <=17 | <=18 | 1 |
| <=17 | <=18 | <=24 | <=25 | 1 |
| >24 | >25 | <=17 | <=18 | 2 |
| <=17 | <=18 | >24 | >25 | 2 |
| >17 | >18 | <=24 | <=25 | 2 |
| <=24 | <=25 | >17 | >18 | 2 |
| >24 | >25 | >17 | >18 | 4 |
| >17 | >18 | >24 | >25 | 4 |
Note: The data/coefficient widths at which implementations
transition to multi-column implementations might be lower than that shown based on
the number of filter coefficients. This ensures that the accumulator width does not
exceed 48 bits, thereby avoiding overflow.
The Data Width threshold is further reduced by a bit when coefficient symmetry is being used by the core, see Filter Symmetry.
The Coefficient Width threshold is further reduced by a bit when symmetric pairs are being used by the core, see Polyphase Interpolator Exploiting Symmetric Pairs.