The AXI4-Stream
interfaces brings standardization and enhances interoperability of AMD
AMD LogiCORE™
IP solutions. Other than general control
signals such as aclk, aclken, and aresetn and the event
outputs, all inputs and outputs to the FIR Compiler are
conveyed on AXI4-Stream channels. A channel consists of
tvalid and tdata
always, plus several optional ports. In the FIR Compiler, the optional ports supported are tready, tlast, and tuser.
Together, tvalid and tready perform a handshake to transfer a message, where the payload is
tdata, tuser, and
tlast. The FIR Compiler operates on the data contained in the input DATA channel
tdata port (s_axis_data_tdata) and outputs the result in the tdata field of the output DATA channel (m_axis_data_tdata). The FIR Compiler
optionally uses the tuser and tlast fields to indicate the phase of a cycle of time-multiplexed
channels. The core also provides the facility to convey a user field within tuser and the tlast signal
from input DATA channel to the output DATA channel with the same latency as for tdata. This facility is intended to ease the use of the FIR Compiler in a system. For example, the FIR Compiler can be used to filter packetized data. In
this example, the tlast has no bearing on the FIR, but
the core can be configured to pass the tlast of the
packetized data channel, saving the system designer the effort of constructing a bypass
path for this information.
For further details on AXI4-Stream Interfaces, see the Vivado Design Suite: AXI Reference Guide (UG1037) and the AMBA® AXI4-Stream Protocol Specification (Arm IHI 0051A).