The standard mode of the DDS Compiler core uses phase truncation, as shown in the following figure.
The integrator (components D1 and A1) computes a phase slope that is mapped to a sinusoid (possibly complex) by the lookup table T1. The quantizer Q1, which simply truncates, accepts the high-precision phase angle θ(n) and generates a lower precision representation of the angle denoted as Θ(n) in the preceding figure. This value is presented to the address port of a lookup table that performs the mapping from phase-space to time.
The fidelity of a signal formed by recalling samples of a sinusoid from a lookup table is affected by both the phase and amplitude quantization of the process. The depth and width of the lookup table affect the phase angle resolution and the amplitude resolution of the signal, respectively. See Spectral Purity Considerations for more details.
Direct digital synthesizers use an addressing scheme with an appropriate lookup table to form samples of an arbitrary frequency sinusoid. If an analog output is required, the DDS presents these samples to a digital-to-analog converter (DAC) and a low-pass filter to obtain an analog waveform with the specific frequency structure. Of course, the samples are also commonly used directly in the digital domain. The lookup table traditionally stores uniformly spaced samples of a cosine and a sine wave. These samples represent a single cycle of a prototype complex sinusoid of length N = 2BΘ(n) and correspond to specific values of the sinusoid argument Θ(n) as follows, where n is the time series sample index:
Quarter-wave symmetry in the basis waveform can be exploited to construct a DDS that uses shortened tables. In this case, the two most significant bits of the quantized phase angle Θ(n) are used to perform quadrant mapping. This implementation results in a more resource efficient implementation because the memory requirements are minimized, offering either fewer FPGA block RAMs or reduced distributed memory. Based on the core customization parameters, the DDS core automatically employs quarter-wave or half-wave symmetry when appropriate.
For shallow tables, FPGA logic resources are actually minimized by storing a complete cycle. No design decisions are required in this context. The AMD adaptive computing tools always produce the smallest core possible.
The rasterized mode of operation of the DDS does not truncate the accumulated phase. Rasterized operation is intended for configurations where the desired frequency is a rational fraction of the system clock (output frequency = system frequency * N/M, where 0 < N < M). Values of M from 9 to 16384 are supported. The SIN/COS LUT is configured accordingly for values from 0 to M-1, which describe a full circle. Because there is no phase truncation in the rasterized mode of operation, there is no need for dither or Taylor correction because these mitigate the effects of phase truncation. In rasterized operation, the phase noise is significantly reduced. Therefore, the output phase angle resolution and amplitude resolution are determined by the LUT table output width alone. In rasterized mode, quadrant symmetry is exploited where applicable to reduce memory use.