The phase dithered and phase truncation DDS have a quantizer Q1 that produces a lower precision Θ(n) by discarding the fractional component of the high precision θ(n). The reason for this quantization step is to keep the size of the lookup memory to a reasonable size. The trade-off is spectral purity. With the availability of DSP slices in FPGAs, it is now practical to use the previously discarded fractional bits to calculate corrections that can be added to the lookup table values to produce outputs with very high SFDR.
Figure 1 through Figure 4 show the simulation results of four different Taylor series corrected DDS simulations. The Taylor series corrected architecture in this example uses a table depth N = 4096 and 18-bit precision samples. However, the precision at the output of the feed-forward error processor is 20 bits. For each plot, the output frequency is different and annotated directly on the plot. A similarly configured phase truncation DDS would produce spurs at – 72 dB and a phase dithered DDS at – 84 dB. The peak spurs for the four plots are –118.25, –118.13, –118.10, and –118.17 dB below the output frequency.
Figure 5 shows a swept frequency Taylor series corrected DDS. The starting frequency for this example is 0.0313 Hz, the final frequency is 0.0813, and there are 100 tones in the sweep. Using this configuration, a phase truncation DDS would produce peak spurs at approximately 72 dB below the output signal and a phase dithered DDS would produce peak spurs at approximately 84 dB below the output signal. As shown in the plot, the Taylor series corrected DDS produced spurs that are all the way down to 118 dB below the output signal. This result is 34 dB better than the phase dithering DDS, 46 dB better than the phase truncation DDS, and still only consumes a single 18 Kb block RAM for the lookup storage. Figure 6 shows another frequency sweep simulation with 35 tones over a broader frequency range.
As shown in the plots, linear correction of the RAM values can extend the SFDR to 118 dB using only a single block RAM and three multipliers. To achieve SFDR beyond 118 dB, it is necessary to deepen the RAM or to use quadratic correction (an extra term of the Taylor series). Because the RAM size would double for each additional 6 dB, the DDS Compiler uses quadratic correction to achieve SFDR values of up to 150 dB. Introducing the extra term of the Taylor series expansion of Sine or Cosine requires an additional multiplier per sine and cosine output and an additional block RAM to both scale and square the phase error.
Optimization of Memory Usage
The Taylor Series correction implementation in the DDS Compiler core typically results in an SFDR higher than that requested in order to guarantee SFDR. This results in extra block RAMs for values of SFDR above 102 dB. However, in many cases, depending on the phase increment values used, a specified SFDR target value of 102 dB provides higher SDFR, but with one 18 K block RAM.