When configured as a SIN/COS LUT only, the Phase Generator is not implemented
and the PHASE_IN signal is input using the input PHASE
channel and transformed into sine and cosine outputs using a lookup table. Efficient
memory usage is achieved by exploiting the symmetry of sinusoid waveforms. The core can
be configured for sine-only output, cosine-only output, or both (quadrature) output.
Each output can be configured independently to be negated. Precision can be increased
using optional Taylor series correction. This exploits DSP slices on FPGA families that
support them to achieve high SFDR with high speed operation.