Resets - Resets - 6.0 English - PG141

The active-Low reset signal, aresetn, is registered within the core to ensure high performance. This signal has the requirement that it must be driven Low for a minimum of two cycles to guarantee that there is no violation of the AXI4-Stream protocol on the core outputs. The registering of reset appears as a delay in entering the reset state, and the signal states after reset differ depending on whether TREADY signals are present.

The following diagram shows the core entering reset when there are no TREADY signals, using a multichannel DDS as an example. The subscript on the valid data outputs indicates a channel number. The true behavioral model outputs X values for TDATA fields during reset. All channel payloads are qualified with their respective TVALID outputs.

The following figure shows the core entering reset when TREADY is present, using a multichannel DDS as an example. The subscript on the valid data outputs indicates a channel number. The reset event forces the FIFOs within the core back into their initial state; no X value is produced by the VHDL RTL-based behavioral model in this case. Again, all channel payloads are qualified with their respective TVALID outputs.