Port Descriptions - Port Descriptions - 6.0 English - PG141

DDS Compiler LogiCORE IP Product Guide (PG141)
Document_ID
PG141
Release_Date
2024-12-11
Version
6.0 English

The DDS Compiler core pinout is shown in the following figure. All of the possible pins are shown, though the specific pins in any instance depend upon parameters specified when the core is generated.

Figure 1. Core Ports
LogiCORE IP DDS Compiler pg141_axi_pinout_x13212 Rectangle.129 Arrow - standard aclk aclk Arrow - standard.2 aclken aclken Arrow - standard.3 aresetn aresetn Arrow - standard.4 s_axis_config_tvalid s_axis_config_tvalid Arrow - standard.7 s_axis_config_tlast s_axis_config_tlast Arrow - standard.8 s_axis_phase_tvalid s_axis_phase_tvalid Arrow - standard.9 s_axis_phase_tready s_axis_phase_tready Arrow - standard.10 s_axis_phase_tdata s_axis_phase_tdata Arrow - standard.11 s_axis_phase_tuser s_axis_phase_tuser Arrow - standard.12 s_axis_phase_tlast s_axis_phase_tlast Arrow - standard.6 s_axis_config_tdata s_axis_config_tdata Arrow - standard.5 s_axis_config_tready s_axis_config_tready Sheet.14 event_s_phase_tlast_missing event_s_phase_tlast_unexpected ev... event_s_phase_tlast_missingevent_s_phase_tlast_unexpectedevent_s_phase_chanid_incorrectevent_s_config_tlast_missingevent_s_config_tlast_unexpectedevent_pinc_invalidevent_poff_invalidevent_phase_in_invalid Sheet.15 m_axis_phase_tvalid m_axis_phase_tready m_axis_phase_tdata m_... m_axis_phase_tvalidm_axis_phase_treadym_axis_phase_tdatam_axis_phase_tuserm_axis_phase_tlast Sheet.16 m_axis_data_tvalid m_axis_data_tready m_axis_data_tdata m_axi... m_axis_data_tvalidm_axis_data_treadym_axis_data_tdatam_axis_data_tuserm_axis_data_tlast Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.33 X13212 X13212 Sheet.35 Sheet.36 Sheet.37

The following table summarizes the pinout of the core. If an active-Low input is required for a specific control pin, an inverter must be placed in the path to the pin and is absorbed appropriately during mapping.

Table 1. Core Signal Pinout
Name Direction Optional Description
aclk I No Rising edge clock
aclken I Yes Active-High clock enable
aresetn I Yes Active-Low synchronous clear. Always takes priority over aclken. aresetn must be driven Low for a minimum of two cycles to reset the core.
s_axis_config_tvalid I Yes TVALID for CONFIG channel
s_axis_config_tready O Yes TREADY for CONFIG channel
s_axis_config_tdata 1 I Yes TDATA for CONFIG channel. See CONFIG Channel TDATA Structure for internal structure and width.
s_axis_config_tlast I Yes TLAST for CONFIG channel. See CONFIG Channel.
s_axis_phase_tvalid I Yes TVALID for input PHASE channel
s_axis_phase_tready O Yes TREADY for input PHASE channel
s_axis_phase_tdata 1 I Yes TDATA for input PHASE channel. See Input PHASE Channel TDATA Structure for internal structure and width.
s_axis_phase_tuser I Yes TUSER for input PHASE channel. See Input PHASE Channel TUSER Structure for internal structure.
s_axis_phase_tlast I Yes TLAST for input PHASE channel. See Input PHASE Channel TLAST Options.
m_axis_phase_tvalid O Yes TVALID for output PHASE channel.
m_axis_phase_tready I Yes TREADY for output PHASE channel.
m_axis_phase_tdata O Yes TDATA for output PHASE channel. See Output PHASE Channel TDATA Structure – Conventional DDS.
m_axis_phase_tuser O Yes TUSER for output PHASE channel. See Output PHASE Channel TUSER Structure.
m_axis_phase_tlast O Yes TLAST for output PHASE channel. See Output PHASE Channel TLAST Options.
m_axis_data_tvalid O Yes TVALID for output DATA channel.
m_axis_data_tready I Yes TREADY for output DATA channel.
m_axis_data_tdata O Yes TDATA for output DATA channel. See Output DATA Channel TDATA Structure.
m_axis_data_tuser O Yes TUSER for output DATA channel. See Output DATA Channel TUSER Structure.
m_axis_data_tlast O Yes TLAST for output DATA channel. See Output DATA Channel TLAST Options.
event_s_phase_tlast_missing O No (but leave unconnected to remove associated circuitry) Asserted when the transfer to the s_axis_phase channel for the last channel (in multichannel configurations) does not have tlast asserted.
event_s_phase_tlast_unexpected O Asserted when TLAST is asserted for a transfer to the s_axis_phase channel which is not for the last channel (in multichannel configurations).
event_s_phase_chanid_incorrect O Asserted when the chanid field (subfield of TUSER in s_axis_phase) does not agree with the internal expectation of channel number.
event_pinc_invalid O Asserted when the value of PINC to be accumulated is out of range. Applies to rasterized configurations only.
event_poff_invalid O Asserted when the value of POFF to be accumulated is out of range. Applies to rasterized configurations only.

event_phase_in_ invalid

 O Asserted when the value of Phase_In is out of range. Applies to rasterized and SIN_COS_LUT configurations only.

event_s_config_tlast_missing

 O Asserted when the last transfer (for the last channel) to the s_axis_config channel is not accompanied with TLAST asserted.

event_s_config_tlast_unexpected

 O Asserted when a transfer to the s_axis_config channel has TLAST asserted when it is not the transfer associated with the last channel.
  1. When in rasterized mode, the input values of PINC, POFF, or PHASE_IN must be between 0 and Modulus-1.