Phase Dithered DDS - Phase Dithered DDS - 6.0 English - PG141

DDS Compiler LogiCORE IP Product Guide (PG141)

Document_ID
PG141
Release_Date
2024-12-11
Version
6.0 English
Note: Phase dithering is only an option in standard mode of operation.

In the phase truncation DDS architecture shown in Figure 1, the quantizer Q1 introduces a phase error in the phase slope by discarding the least significant part of the high-precision phase accumulator. The phase error due to the discarded fractional part of the address count is a periodic series which results in an undesired spectral line structure. The following figure provides an example of this process for a DDS with a table depth N = 1024 and table sample precision of 16 bits.

(a)
Phase error generated by taking the difference between the quantizer input and output signals
(b)
Output time series
(c)
Signal output spectrum
Figure 1. DDS Plots (1024 Deep Lookup Table, 16-Bit Samples, Output Frequency 0.333 Hz)

Observe in (a) the periodic sawtooth structure of the phase error signal. The line spectrum associated with this correlated error sequence is impressed on the final output waveform and results in spectral lines in the synthesizer output spectrum. These spurious components can be clearly seen in (c).

This structure can be suppressed by breaking up the regularity of the address error with an additive randomizing signal. This randomizing sequence, called dither, is a noise sequence, with variance approximately equal to the least significant integer bit of the phase accumulator. The dither sequence is added to the high-precision accumulator output prior to quantization by Q1.

The dithered DDS supplies, approximately, an additional 12 dB of spurious free dynamic range (SFDR) in comparison to a phase truncation design. This is achieved by spreading the spectral energy of the phase error signal. The additional logic resources required to implement the dither sequence generator are not significant.

To provide S dB of spur suppression using a phase truncation DDS, as referenced to the 0 dB primary tone, the internal lookup table must support at least S/6 address bits. To achieve this same performance using the dithered architecture requires two fewer address bits, minimizing the number of block RAMs (or logic slices for a distributed memory implementation) used in the FPGA implementation. In summary, for a dithered DDS implementation, the number of address bits needed to support dB spur suppression is equal to S/6 – 2.

The following two figures provide the results for several dithered DDS simulations. The first figure shows eight simulations for a complex dithered DDS employing a table depth N = 4096 and 16-bit precision samples. For each plot the output frequency is different and is annotated on the plot. A phase truncation design would typically generate output spurs 72 dB below the output frequency, independent of the actual value of the output frequency. Indicated on each of the plots by the parameter A is the peak spur level achieved for the simulation. The eight spurs are –88.12, –88.22, –86.09, –88.80, –87.21, –87.55, –87.83, –87.12 dB below the output frequency. The worst case value of –86.09 is 14.09 dB better than a similarly configured phase truncation DDS.

Figure 2. Dithered DDS Simulations (DDS Configuration N = 4096, Bs = 16)

The eight plots are spectral domain representations for eight different output frequencies. Each plot is annotated with the peak spur.

To achieve this same SFDR by extending the table length of a phase truncation design would require increasing the table depth by more than a factor of four.

The following figure provides one more dithered DDS simulation where the output frequency is swept over a band of frequencies. The spectrum for each discrete tone in the sweep band is overlaid to construct the final plot. The sweep start frequency, end frequency, number of tones in the sweep, and DDS configuration are annotated on the plot.

Figure 3. Example Plot for Dithered DDS Simulation with Frequency Sweep

In the preceding figure, the synthesized signal is swept over a range of frequencies starting from 0.0311 to 0.0415 Hz. There are 10 tones in the sweep separated in frequency by 0.00104 Hz. In this example, the phase truncation DDS would produce peak spurs at –72 dB with respect to the 0 dB primary signal. The dithered DDS provides approximately 12 dB better performance with the peak spur –84 dB below the output signal.

A further advantage of the dithered DDS is that the spectral line structure present in a phase truncation design is removed and the out-of-band signal is significantly whitened. This white broadband noise floor is more desirable than the line structured spectrum. In digital communication receivers that use a DDS for generating mixing signals for performing channelization functions, the spurs in a phase truncation DDS can act as low-level mixing tones and cause undesirable spectral contamination of the desired channel. For virtually all applications, the preferred implementation is the dithered DDS.