This section details the performance information for various core configurations.
Latency
The latency of the core can be specified through the user interface in the Vivado Integrated Design Environment (IDE), or it can be automatically set to the optimum value based upon the optimization goal.
For streaming inputs (s_axis_phase_t*) the latency
specifies the minimum number of cycles between input and the associated output.
For configuration inputs, the latency is the minimum latency from the first cycle
aresetn becomes inactive until a valid output. The latency from
configuration channel inputs to output channel outputs is not deterministic because
configuration inputs are synchronized to the internal channel counter phase, thus
introducing a delay which is unknown external to the core.
CE and
TVALID on input are not both used to control data
into the core, because this can lead to obscure latency. For instance, if
TREADY is not used, data samples are pushed through the core by
TVALID on input, and setting TVALID Low freezes data in
transit much like clock enable. It is recommended that full AXI4-Stream
protocol is used where latency is variable, but no data is lost. If deterministic latency is
required, fix either CE or TVALID High and control data
flow using the other.Throughput
The DDS Compiler core supports full throughput in all configurations (one output for every cycle).