Optional Pins - Optional Pins - 6.0 English - PG141

DDS Compiler LogiCORE IP Product Guide (PG141)

Document_ID
PG141
Release_Date
2024-12-11
Version
6.0 English

Certain inputs and outputs can be disabled to save resources.

Has Phase Out
When checked the core has the output PHASE channel.
ACLKEN
When checked the core has an aclken (active-High clock enable) port.
ARESETn
When checked the core has an aresetn (active-Low synchronous reset) port.