Select whether latency should be configured automatically by the Vivado IDE or manually:
- Auto
- Causes the DDS to be pipelined for optimal performance (taking into account the optimization goal).
- Configurable
- Where optimal performance is beyond requirements, latency can be set to
configurable and a smaller value of latency selected. This reduces the number of
pipeline stages and generally results in resource savings. A minimum value of
latency is imposed, where a cycle of latency arises from each of the following
sources:
- Streaming phase increment
- Block ROM within SIN/COS LUT (this can be avoided if you select Distributed ROM).
- Block ROM within second order Taylor series correction (used for SFDR above 120 dB).
Note: When TREADY is selected the AXI interfaces buffer data as a FIFO. This buffering results in non-deterministic latency. However, this action can only increase in latency. In this case, the minimum latency possible is six cycles plus the minimum latency described above.