Latency Changes - Latency Changes - 6.0 English - PG141

DDS Compiler LogiCORE IP Product Guide (PG141)

Document_ID
PG141
Release_Date
2024-12-11
Version
6.0 English

In version 6.0, latency and initial conditions have changed for some configurations to ensure compliance with the equation for PHASE_OUT.

The latency of DDS Compiler v6.0 is different compared to v4.0 and greater in general. The update process cannot account for this and guarantee equivalent performance.

Note: When in blocking mode (that is, TREADY handshaking is present), the latency of the core is variable, so only the minimum possible latency can be determined. When in non-blocking mode (no TREADY), the latency of the core is as shown in the latency field of the Vivado IDE and is constant.