Instructions for Minimum Change Migration - Instructions for Minimum Change Migration - 6.0 English - PG141

Parameters

Most parameters remain unchanged. Uncheck output TREADY. All other new parameters default as required for legacy operation.

If the CHANNEL output was used, set the DATA Output TUSER setting to Chan_ID_Field.

Ports

Rename ports as described in Port Changes.

• WE, REG_SELECT, ADDR and DATA are replaced by the CONFIG channel, where WE is equivalent to TVALID, ADDR has no equivalent, but is replaced internally by an incrementing count with s_axis_config_tlast denoting the last transfer of the TDM sequence, DATA(T-1:0) is replaced by s_axis_config_tdata (see CONFIG Channel TDATA Structure). REG_SELECT is no longer required, because both PINC and POFF can be written in a single transfer.
• PINC_IN and POFF_IN are mapped to s_axis_phase_tdata as described in Input PHASE Channel TDATA Structure. Connect s_axis_phase_tvalid to logical 1.
• SINE(P-1:0) and COSINE(P-1:0) are mapped to m_axis_data_tdata as described in Output DATA Channel TDATA Structure. RDY becomes s_axis_data_tvalid.
• CHANNEL(N-1:0) becomes m_axis_data_tuser (N-1:0).
• PHASE_OUT(W-1:0) becomes m_axis_phase_tdata (W-1:0) as described in Output PHASE Channel TDATA Structure – Conventional DDS.

Miscellaneous Changes

The synchronous, active-Low reset pin aresetn must be driven Low for a minimum of two clock cycles to correctly reset the core. The reset is registered within the core, causing some delay between the assertion/deassertion of aresetn and the effect being seen on the interface.

Performance

To achieve equivalent performance to v4.0, Latency should be set to the original latency value plus 1. Alternatively, set Latency to be the same as Latency for v4.0, but there might be drop in performance. Resource allocation for this configuration is greater than v4.0 in flip-flop count by approximately the number of bits in any fields in s_axis_phase_tdata.