The input PHASE channel can be configured to have no TLAST, to have a vector framing TLAST, or to have a packet framing TLAST.
When Vector Framing is selected, TLAST is expected to indicate the last channel in a TDM cycle of channels. If TLAST does not match the internal expectation of when TLAST should arrive, one of two event signals is asserted for a clock cycle.
When Packet Framing is selected, the core does not have any expectation of the timing of TLAST so the event signals are not present, but TLAST is conveyed to the output channels with the same latency as the TDATA input.