- Phase Increment Programmability
- Selects the means by which the PINC value is set.
- Fixed
- PINC is fixed at generation time and cannot be changed at runtime. Fixed requires minimal resource.
- Programmable
- PINC value can be changed at runtime using the CONFIG channel. This is recommended when the DDS frequency is to change between modes of operation.
- Streaming
- PINC value is taken directly from the input PHASE channel. This is recommended when the PINC value has to change often, or when frequency modulation is required, for example.
- Resync
- When selected, the s_axis_phase channel has a RESYNC field. This bit, when asserted, mutes the accumulated phase for the channel in question. The value of the accumulated phase for that cycle is the value of PINC accompanying the RESYNC assertion, plus the POFF value.
- Phase Offset Programmability
- Selects the means by which the POFF value is set.
- None
- No phase offset facility and the required hardware is not generated. This saves FPGA resources.
- Fixed
- PINC is fixed at generation time and cannot be changed at runtime.
- Programmable
- POFF value can be changed using the CONFIG channel. This is recommended when the DDS phase is to change between modes of operation.
- Streaming
- POFF value can be changed using the input PHASE channel. This is recommended when the POFF value has to change often, or when phase modulation is required, for example.
- Output
-
- Output_Selection
- The DDS can have a quadrature SINE and COSINE field in the
m_axis_data_tdatabus, or only one of these two fields. See Output DATA Channel TDATA Structure form_axis_data_tdatainternal structure. - Polarity
- The SINE and COSINE fields of
m_axis_data_tdatacan be inverted. This allows conversion of a DDS used as a transmitter mixer to a receiver mixer, using conjugated outputs; hence both instantiations are identical except for the values of the two selections here.- Negative Sine
- Checking this selection results in the SINE field being negated at runtime.
- Negative Cosine
- Checking this selection results in the COSINE field being negated at runtime.
- Amplitude Mode
- This selection allows for one of two amplitudes from the DDS.
- Full Range
- Aimed at communications applications where the maximum amplitude within the two’s complement representation is desired, but the value of amplitude is less important due to the expectation of automatic gain control. The target amplitude for full range mode is 1 – 2 – (Output Width – 2) for non-Taylor modes, whereas for Taylor mode the amplitude varies between this value and 1. Here, amplitude is normalized to the output width with the binary point in the first place. An 8-bit output would have a binary amplitude of 100000000 – 10 giving values between 01111110 and 11111110 corresponding to just less than 1 and just more than –1 respectively.
- Unit Circle
- For applications where the value of the DDS output amplitude is
important; for example, for FFT twiddle factor
generation. When Unit Circle, the DDS output
amplitude is half full range (that is, values range from
01000 .. (+0.5). to 110000 .. (-0.5)). As the amplitude
is reduced over Full
Range by a factor of 2, the
SDFR is reduced by 6 dB. Increase SFDR or output width
to accommodate this requirement.Note: Only Unit Circle applies if floating point is selected as the SIN/COS Output Type
Implementation Options
- Memory Type
- This controls the implementation of the SIN/COS LUT. The Auto setting selects distributed ROM for small cases where the table can be contained in a single layer of memory, and selects block ROM for larger cases (that is, Distributed ROM is selected when Phase Width≤ 5 bits). This selection can be overridden by selecting Distributed ROM or Block ROM explicitly.
- Optimization Goal
- In some cases, circuit clock speed can be increased at the expense of extra pipelining registers. This selection controls whether the implementation decisions target highest speed or lowest resource.
- DSP48 Use
- This controls the implementation of the phase accumulator and following addition stages (for phase offset and/or dither noise addition). When set to Minimal, the phase accumulator and following stages are implemented in FPGA logic. When set to Maximal, all is implemented using DSP slices. In the single channel case, the DSP slice can also provide the register to store programmable phase increment and/or phase offset and thereby save further fabric resources. This is not done if either Phase Increment or Phase Offset is set to Streaming, and only when the Optimization Goal is Area. When this optimization is performed, the initial value of the PINC and/or POFF register must be zero. This is enforced by the Vivado IDE by setting the initial value of PINC and/or POFF to zero and disabling entry.