Hardware Parameters - Hardware Parameters - 6.0 English - PG141

DDS Compiler LogiCORE IP Product Guide (PG141)

Document_ID
PG141
Release_Date
2024-12-11
Version
6.0 English
Phase Width
Sets the width of the PHASE_OUT field within m_axis_phase_tdata, the phase field within s_axis_phase_tdata when the DDS is configured to be a SIN/COS LUT only, the phase accumulator, associated phase increment and offset registers, and the phase field in s_axis_config_tdata. For rasterized mode, the phase width is fixed as the number of bits required to describe the valid input range [0, Modulus-1], that is log2 (Modulus-1) rounded up.
Output Width
Only enabled when the DDS or SIN/COS LUT part is selected (because it is not required by the Phase Generator part), and when the output type is configured to integer. Sets the width of SINE and COSINE fields within m_axis_data_tdata. The SFDR that this provides is dependent on the noise shaping option previously selected. The Output Width is set to 32 if floating point is selected as the output type. The equations in the following table can be used to estimate the SFDR that can be achieved:
Table 1. Calculation of SFDR for Given Noise Shaping
Noise Shaping SFDR
None, Dither SFDR = Output Width x 6
Taylor SFDR = (Output Width - 1) x 6
Note: When using Partitioning the maximum SFDR is ~141dB.