- The Phase Generator and SIN/COS LUT can be generated individually or together with optional dither to provide a complete DDS solution.
- Rasterized feature eliminates phase noise from phase truncation.
- Sine, cosine, or quadrature outputs
- Integer or float sine/cosine outputs
- Optional per-channel resynchronization of accumulated phase
- Lookup table can be stored in distributed or block RAM
- Optional phase dithering spreads the spectral line energy for greater spurious-free dynamic range (SFDR)
- Phase dithering, Partitioning (float), or Taylor series correction (integer) options provide high dynamic range signals using minimal FPGA resources.
- Supports SFDR from 18 dB to 150 dB.
- Up to 16 independent time-multiplexed channels
- Fine frequency resolution using up to 48-bit phase accumulator with DSP slice or FPGA logic options
- 3-bit to 26-bit signed (integer) or 32-bit (single precision float) output sample width