In standard mode, with a single-channel DDS, a 1 MHz system clock, and a frequency resolution of 1 Hz, phase width is 20 bits. To synthesize an output of 23.4 kHz, an output frequency value of 0.0234 MHz must be entered into the user interface, which then returns a value of 5FD8 in hexadecimal, which is 24536 in decimal.
This gives a synthesized frequency of 24536/220 *1 MHz = 23399.35 Hz.
If the application requires this frequency to be modulated by one of eight phase offsets, the phase offset bus need only have 3-bit precision, but these must be the top 3 bits of the phase offset input. Hence, the phase offset of one eighth of a cycle would be entered as 0.125 in the user interface. This returns a value of 20000 (hex). This could be entered on the 3-bit bus as 001 (binary).