Demonstration Test Bench in Detail - Demonstration Test Bench in Detail - 6.0 English - PG141

The demonstration test bench performs the following tasks:

• Instantiate the core
• Generate a clock signal
• Drive the core input signals to demonstrate core features
• Check that the core output signals obey AXI protocol rules (to keep the test bench simple, data values are not checked)
• Provide signals showing the separate fields of AXI TDATA and TUSER signals

The operations performed by the demonstration test bench are appropriate for the configuration of the generated core:

• If phase increment and offset are fixed:
  • Run to produce sine / cosine / phase outputs
• If phase increment and/or offset are programmable, and neither is streaming:
  • Program an initial configuration
  • Run to produce sine / cosine / phase outputs
  • Program a different configuration
  • Run again to produce sine / cosine / phase outputs
• If one of phase increment or offset are streaming and the other is fixed:
  • Stream in constant phase increment or offset to produce sine / cosine / phase outputs
  • If phase offset is streaming, stream in incrementing phase offset to produce higher frequency sine / cosine / phase outputs
• If one of phase increment or offset are streaming, and the other is programmable:
  • Program an initial configuration
  • Stream in constant phase increment or offset to produce sine / cosine / phase outputs
  • If phase offset is streaming, stream in incrementing phase offset to produce higher frequency sine / cosine / phase outputs
  • Continue streaming in phase increment or phase offset, and simultaneously program a different configuration
• If phase increment and offset are both streaming:
  • Stream in constant phase increment and zero phase offset to produce sine / cosine / phase outputs
  • Stream in zero phase increment and incrementing phase offset to produce sine / cosine / phase outputs
• For SIN/COS LUT only:
  • Stream in incrementing phase to produce sine / cosine outputs
• For all configurations:
  • Demonstrate back pressure by deasserting TREADY of master channels (if TREADY is present)
  • Demonstrate use of clock enable (if present)
  • Demonstrate use of reset (if present)