- Configuration Options
- The full DDS or optionally the Phase Generator part or SIN/COS LUT part
can be generated.
- Phase Generator and SIN/COS LUT
- DDS is provided by combining Phase Generator and SIN/COS LUT with an optional dither circuit.
- Phase Generator only
- Only the phase generator is provided.
- SIN/COS LUT only
- Only the SIN/COS LUT with optional Taylor series correction (integer) or partitioning (float) circuit is provided.
- System Requirements
-
- System Clock
- The frequency at which the DDS core is clocked. The value provided
influences architectural choices, and is used to calculate the value of phase
increment from output frequency (it is the relative value of output frequency to
system clock that specifies phase increment, and so doubling system clock while
maintaining output frequency results in a doubling of phase increment).Important: The specified clock rate might not be achievable by the final implementation, because this depends on the FPGA family and how much is being packed into the device.
- Number of Channels
- The DDS and phase generator can support up to 16 channels. The channels are time-multiplexed, which reduces the effective clock frequency per channel.
- Mode of Operation
- The DDS supports standard mode, where the accumulated phase can be truncated before being used to access the SIN/COS LUT, or rasterized mode, which can be used when the desired frequencies and system clock are related by a rational fraction. See Theory of Operation for more details.
- Modulus (rasterized mode only)
- Describes the relationship between the system clock frequency and the desired frequencies. See Theory of Operation for details.
- Frequency per Channel (Fs)
- Because of time division multiplexing, the effective system clock to each channel is the real system clock divided by the number of channels.
- SIN/COS Output Type
- The DDS supports either integer or floating point mode for SIN/COS generation.
- Parameter Selection
- DDS key parameters can be specified using System Parameters, which are aimed at system architects (frequency domain parameters) or Hardware Parameters, which are aimed at hardware engineers (time-domain parameters). The Phase Generator and SIN/COS LUT are only specified in terms of hardware parameters.