This event signal is asserted for a single clock cycle when the CIC Compiler sees
s_axis_data_tlast High on any incoming data sample that does
not correspond to the last channel.
This signal is intended to show a mismatch between the CIC Compiler and the upstream data source with regard to channel synchronization.
If there are multiple unexpected highs on s_axis_data_tlast, then
this signal is asserted for each of them. The event pin is only available when the
core is configured to have multiple channels.