In addition to all the parameterization values of the core, the summary page displays:
- Bits per Stage
- The number of bits used in each of the stages of the CIC Compiler filter implementation. These numbers are computed based on the register growth analysis presented in An Economical Class of Digital Filters for Decimation and Interpolation.
- Latency
- The input to output latency in the CIC Compiler core implementation. When HAS_DOUT_TREADY is TRUE then the actual latency might be greater than reported because throughput can be controlled by the system connected to the Data Output Channel. The value reported by the Vivado Design Suite is the minimum latency.