Port Changes - Port Changes - 4.0 English - PG140

CIC Compiler v4.0 LogiCORE IP Product Guide (PG140)

Document_ID
PG140
Release_Date
2026-07-22
Version
4.0 English

The following table details the changes to port naming, additional or deprecated ports and polarity changes from v2.0 to v4.0:

Table 1. Port Changes from Version 2.0 to Version 4.0
Version 2.0 Version 4.0 Notes
CLK ACLK Renamed
CE ALCKEN Renamed
SCLR ARESETN Renamed

Polarity change (now active-Low)

Minimum length now two clock cycles

DIN S_AXIS_DATA_TDATA Renamed
ND S_AXIS_DATA_TVALID Renamed
RFD S_AXIS_DATA_TREADY Renamed
S_AXIS_DATA_TLAST New signal
RATE S_AXIS_CONFIG_TDATA Renamed
RATE_WE S_AXIS_CONFIG_TVALID Renamed
S_AXIS_CONFIG_TREADY New signal
DOUT M_AXIS_DATA_TDATA Renamed
RDY M_AXIS_DATA_TVALID Renamed
M_AXIS_DATA_TREADY New signal

Optional

M_AXIS_DATA_TLAST New signal
CHAN_SYNC M_AXIS_DATA_TUSER Renamed
CHAN_OUT M_AXIS_DATA_TUSER Renamed
event_tlast_missing New signal
event_tlast_unexpected New signal
event_halted New signal