Pipelined CIC Decimator - Pipelined CIC Decimator - 4.0 English - PG140

To support high system clock frequencies, the CIC decimator is implemented using the pipelined architecture shown in the following figure.

The CIC datapath undergoes internal register growth that is a function of all the design parameters: N, M, and R, in addition to the input sample precision B. As shown in An Economical Class of Digital Filters for Decimation and Interpolation, the output bit width of a CIC decimator with full precision is given by:

where indicates the ceiling operator. The CIC Compiler supports both full and limited precision output. For full precision, the CIC decimator implementation uses B_max bits internally for each of the integrator and differentiator stages. This introduces no quantization error at the output. For limited precision (that is, output bit width less than B_max), the registers in the integrator and comb stages are sized to limit the quantization noise variance at the output. Consequently, the hardware resources in a CIC decimator implementation can be reduced when using limited precision output at the cost of quantization noise. This ability to trade off resources and quantization noise is important to achieve an optimum implementation.