Interpolator - Interpolator - 4.0 English - PG140

The following figure shows the timing for a CIC interpolator with an up-sampling factor R = 4. A new input sample can be accepted by the core every fourth cycle of the clock. After the initial start-up latency, m_axis_data_tvalid is asserted, and a new filter output is available on every subsequent clock edge. For every input delivered to the filter core, four output samples are generated. At point A in the waveform, the master provides data before the CIC Compiler requests it. The master has to continue supplying this data until the CIC Compiler accepts it (at point B). At point C in the waveform, the CIC Compiler is ready to accept data but the master does not provide it. The CIC Compiler continues to ask until it is provided (point D).

The following figure shows the same filter configuration with an input sample period of 8.

Multichannel Interpolators can be configured to consume data in two timing modes, Block and Streaming:

• Block mode: samples for the channels are consumed back-to-back. That is, the data for channel N+1 is consumed immediately after the data for channel N.
• Streaming mode: samples for the channels are consumed evenly over the entire sample period.

Refer to the following figures for more information.

These modes operate independently of the AXI4 interface and they refer to the part of the core that processes the data. When HAS_DOUT_TREADY = 1 the AXI4 interface can buffer data in the Data Input Channel which means that streaming mode might start to behave like block mode. Until its buffer is full, the Data Input Channel requests back-to-back data (using s_axis_data_tready) even though the processing part of the core does not consume it immediately.

The following figure shows the timing for a multichannel CIC interpolator with a rate change R = 4. In this example the interpolator filter handles two channels of data and uses the block-based interface. The input DIN shows the time-multiplexed samples with labels to indicate the corresponding channel number. The output DOUT shows the time-multiplexed data samples.

The following figure shows the same filter configuration using the streaming interface.

The following figure shows the timing for a CIC interpolator with programmable rate. In the timing diagram, the interpolator is shown with an initial up-sampling rate value of 4. After some time, the up-sampling rate is changed to 7 by setting the RATE field to 7 and asserting s_axis_config_tvalid at point A in the waveform. As the rate is only applied when the next sample for the first channel is accepted by the CIC Compiler, s_axis_config_tready deasserts until the rate change is applied (point B). In this example, the sample (x₁) following point A is for the second channel, so the rate is not applied here. This prevents the upstream master providing a new rate which cannot be accepted by the core.