Implementation Options - Implementation Options - 4.0 English - PG140

The Implementation tab is used to define implementation options. REfer to Implementation Options in the Vivado IDE for complete parameter details.

Has ARESETN

Specifies whether the core has a reset pin (the equivalent of selecting the Has ARESETN option in the Vivado IDE).

Has ACLKEN

Specifies whether the core has a clock-enable pin (the equivalent of selecting the Has ACLKEN option in the Vivado IDE).

Has DOUT TREADY

Specifies whether the Data Output Channel has a TREADY pin (the equivalent of selecting the HAS_DOUT_TREADY option in the Vivado IDE).

FPGA Area Estimation

Refer to System Generator documentation for details.