Implementation Options - Implementation Options - 4.0 English - PG140

CIC Compiler v4.0 LogiCORE IP Product Guide (PG140)

Document_ID
PG140
Release_Date
2026-07-22
Version
4.0 English
Input Data Width
Number of bits for input data. The valid range of this parameter is 2 to 32. In IP integrator, this parameter is auto-updated.
Quantization
Type of quantization for limited precision output, Full Precision or Truncation. This quantization applies only to the output and is not applied in the intermediate stages of the CIC Compiler filter.
Output Data Width
Number of bits for output data. The valid range of this parameter is up to 48 bits with the minimum value set to the input data width.
Use Xtreme DSP Slice
Use DSP hardware primitive slices in the filter implementation.
Use Streaming Interface
Specifies if a streaming interface is used for multiple channel implementations. Refer to Decimator, for further details.
Has DOUT TREADY
Specifies if the Data Output Channel has a TREADY signal.
ACLKEN
Determines if the core has a clock enable input (aclken).
ARESETN
Determines if the core has an active-Low synchronous clear input (aresetn).
Note:
  • The signal aresetn always takes priority over aclken, that is, aresetn takes effect regardless of the state of aclken.
  • The signal aresetn is active-Low.
  • The signal aresetn needs to be held active for at least two clock cycles. This is because, for performance, aresetn is internally registered before being fed to the reset port of primitives.