Latency Changes
- HAS_DOUT_TREADY = 0
- The latency is identical to the equivalent configuration of v2.0.
- HAS_DOUT_TREADY = 1
- The latency is variable, with only the minimum possible latency being determinable. The latency is a minimum of three cycles longer than the equivalent configuration of v2.0. The update process cannot account for this and guarantee equivalent performance.
Simulation
Starting with CIC Compiler v4.0 (2013.3 version), behavioral simulation models are replaced with IEEE P1735 Encrypted VHDL. The resulting model is bit and cycle accurate with the final netlist. For more information on simulation, see the Vivado Design Suite User Guide: Logic Simulation (UG900).