Demonstration Test Bench in Detail - Demonstration Test Bench in Detail - 4.0 English - PG140

The demonstration test bench performs these tasks

• Instantiate the core
• Generate a clock signal
• Drive the core clock enable and reset input signals (if present)
• Drive the core input signals to demonstrate core features (see the following sections for details)
• Provide signals showing the separate fields of AXI4 TDATA and TUSER signals

The demonstration test bench drives the core input signals to demonstrate the features and modes of operation of the core. The test bench drives a sine wave into the CIC core. In multichannel mode, the frequency of the sine wave increases with each channel. The output of the core shows the same sine wave (or waves in multichannel mode) but in a decimated or interpolated format. Alias signals are used to decode the AXI4 channels and allow easy viewing of the input and output data.

The operations performed by the demonstration test bench are appropriate for the configuration of the generated core, and are a subset of the following operations (in order):

1. Asserts reset at the start of the test. Only available when the core is configured with a reset (HAS_ARESETN = TRUE).
2. Sends data to CIC Compiler core with no waitstates. The upstream master supplies data to the CIC Compiler core at the input sample rate.
3. Sends data to CIC Compiler core with waitstates. The upstream master adds random waitstates to the input samples by deasserting s_axis_data_tvalid.
4. Asserts and deasserts clock enable (aclken) on alternating clock cycles. This has the effect of halving the input sample rate. Only available when the core is configured with a clock enable (HAS_ACLKEN = TRUE).
5. Changes the rate of the core. Only available in programmable rate cores.
6. Injects waitstates on Data Output Channel. The downstream slave keeps m_axis_data_tready deasserted for random periods of time. Only available when the core is configured with a TREADY on the Data Output Channel (HAS_DOUT_TREADY = TRUE).