The timing for a CIC decimator with a down-sampling factor R = 4 is shown in the following figure. In this example, the core is not oversampled and can accept a new input sample on every clock edge. Some number of clock cycles after the first input sample has been written to the filter, m_axis_data_tvalid is asserted by the filter to indicate that the first output sample is available. This time interval is a function of the down-sampling factor R and a fixed latency that is related to internal pipeline registers in the core. The number of pipeline stages depends on the core parameters. After the first output sample has been produced, subsequent outputs are available every R clock cycles.
The following figure shows the timing for the same filter configuration with an input sample period of 3. At point A in the waveform, the CIC Compiler is ready to accept data but the master does not provide it. The CIC Compiler continues to ask until it is provided (point B). At point C in the waveform, the master provides data before the CIC Compiler requests it. The master has to continue supplying this data until the CIC Compiler accepts it (at point D).
Multichannel Decimators can be configured to produce data in two timing modes, Block and Streaming:
- Block mode: samples for the channels are produced back-to-back. That is, the data for channel N+1 is produced immediately after the data for channel N.
- Streaming mode: samples for the channels are produced evenly over the entire sample period.
These modes operate independently of the AXI4
interface and they refer to the part of the core that processes the data. When HAS_DOUT_TREADY =
1 the AXI4 interface can buffer data in the Data Output Channel
which means that streaming mode can start to behave like block mode. If the downstream system
does not consume data when it first becomes available, the Data Output Channel can start to fill.
In this case, the Data Output Channel produces back-to-back data (using m_axis_data_tvalid) until the buffer in the channel is empty, even though the
processing part of the core did not produce it back-to-back.
The following figure shows the timing for a multichannel CIC decimator with a rate change R = 4. In this example the decimator filter handles three channels of data and is configured to use the block-based interface. The input to the decimator DIN shows the time-multiplexed samples with labels to indicate the corresponding channel number. The output of the decimator DOUT shows the time-multiplexed data.
The following figure shows the timing for the same filter configuration using the streaming interface.
The following figure shows the timing for a CIC decimator with programmable
rate. In the timing diagram, the decimator is shown with an initial down-sampling rate value of
4. After some time, the down sampling rate is changed to 7 by setting the value in the RATE field
to 7 and asserting s_axis_config_tvalid at point A in the waveform. As the rate
is only applied when the next sample is accepted by the CIC Compiler, s_axis_config_tready deasserts for a cycle while the rate change is applied. This
prevents the upstream master providing a new rate which cannot be accepted by the core.