Symbol data to be processed is loaded into the CIC Compiler core using the Data Input Channel. Processed symbol data is unloaded using the Data Output Channel. Both of these use the AXI4-Stream protocol. The following figure shows the basics of this protocol.
TVALID is driven by the channel master to show
that it has data to transfer, and TREADY is driven by the
channel slave to show that it is ready to accept data. When both TVALID and TREADY are High, a transfer takes
place. Points A in the diagram show clock cycles where no data is transferred because neither
the master or the slave is ready. Point B shows two clock cycles where data is not transferred
because the Master does not have any data to transfer. This is known as a master waitstate.
Point C shows a clock cycle where no data is transferred because the slave is not ready to
accept data. This is known as a slave waitstate. Master and slave waitstates can extend for
any number of clock cycles.
When the master asserts TVALID High, it must
remain asserted (and the associated data remain stable) until the slave asserts TREADY High.
The preceding figure shows the loading of 8 samples. The upstream master
drives TVALID and the CIC Compiler drives TREADY. In this case, both the master and the CIC Compiler insert
waitstates.
The preceding figure also shows the unloading of 8 samples. The CIC Compiler
drives TVALID and the downstream slave drives TREADY. In this case, both the CIC Compiler and the slave insert
waitstates. This only applies when the core is configured to have a TREADY port on the Data Output Channel (XCO HAS_DOUT_TREADY = TRUE). When this is
false, there is no TREADY signal on the Data Output Channel
and the downstream slave cannot insert waitstates. The slave must be able to respond
immediately on every clock cycle where the CIC Compiler produces data (m_axis_data_tvalid asserted High). If the slave cannot respond immediately, then
data is lost.
For multiple-channel implementations, the CIC Compiler core supports
time-multiplexed input and output. The filter input data in the DATA field of the Data Input Channel TDATA vector
(s_axis_data_tdata) is expected to have an ordered,
time-multiplexed format. The core produces time-multiplexed output data on the DATA field of the Data Output Channel TDATA vector (m_axis_data_tdata). Two additional
fields are included in multichannel implementation. The CHAN_SYNC field in the Data Output Channel TUSER
vector (m_axis_data_tuser) indicates the output corresponding
to the first channel in the time-multiplexed stream. The CHAN_OUT field in the Data Output Channel TUSER
vector (m_axis_data_tuser) contains the channel number for
each output in the time-multiplexed steam.
For programmable rate implementations, the RATE field in the Configuration
Channel TDATA vector (s_axis_config_tdata) controls the rate change in the CIC Compiler filter core. The
RATE field is sampled when s_axis_config_tvalid and s_axis_config_tready are both asserted High. The core uses the new
RATE value on the next input sample, for a single channel
implementation, or the next input to the first channel, for multiple channel implementations.
All of the waveforms are shown with HAS_DOUT_TREADY = FALSE. Setting this to TRUE allows the downstream data slave to delay the data output of the CIC Compiler. It also allows the Data Input Channel to buffer samples so that they can be supplied at a faster rate than the core can process them.
To simplify the waveforms, the following field aliases are used
-
DINis used to represent the DATA field in the Data Input ChannelTDATAvector (s_axis_data_tdata) -
DOUTis used to represent the DATA field in the Data Output ChannelTDATAvector (m_axis_data_tdata) -
CHAN_SYNCis used to represent the CHAN_SYNC field in the Data Output ChannelTUSERvector (m_axis_data_tuser) -
CHAN_OUTis used to represent the CHAN_OUT field in the Data Output ChannelTUSERvector (m_axis_data_tuser) -
RATEis used to represent the RATE field in the Configuration ChannelTDATAvector (s_axis_config_tdata)