Revision History - 8.0 English - PG138

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)
Document ID
PG138
Release Date
2025-12-09
Version
8.0 English

The following table shows the revision history for this document.

Section Revision Summary
12/09/2025 Version 8.0
Changes from v7.2 to v8.0 Added new section.
Customizing the Subsystem to Share Resources across Multiple Instances Updated figures and added options: Start_With_new_Quad and Customized_Connections.
For Versal Adaptive SoC Designs Updated the instructions.
Customizing the Subsystem in the Vivado IDE Updated figures.
Features Updated the section. Added support for Versal Gen 2 Adaptive SoCs.
Feature Summary Updated the section.
06/05/2023 Version 7.2
Clocking Added a table.
11/15/2023 Version 7.2
Editorial updates Rebranding updates.
05/17/2023 Version 7.2
GMII or RGMII interface Added the topic.
Ethernet System Interface Updated the table.
11/16/2022 Version 7.2
N/A Added Versal devices support.
05/11/2022 Version 7.2
IO Delay Calibration Ports for Ethernet RGMII Interface Added the topic.
20/03/2021 Version 7.2
N/A Added support for Versal Adaptive SoC.
01/14/2021 Version 7.2
Dynamic Switching Signal Port Added the topic.
Design Flow Steps Added support for Versal Adaptive SoC.
06/24/2020 Version 7.2
Latency Values for the 1588 Enabled Configuration Added the topic.
Design Flow Steps Updated GUI details.
Functional Description Updated the topic.
05/22/2019 Version 7.1
N/A
  • Updated Figure 2-10.
  • Added note to Table 2-23 and Table 2-24.
  • Updated Table 2-29.
  • Updated Figure 2-25.
12/05/2018 Version 7.1
N/A
04/04/2018 Version 7.1
N/A
  • Updated the SGMII Auto-Negotiation section in Chapter 2, Product Specification.
  • Added the .h Header File section in Chapter 2, Product Specification.
  • Added a new paragraph to the Clocking section of Chapter 3, Designing with the Subsystem.
  • Removed a paragraph about the Include Shared Logic in IP Example Design configuration before Figure 4-5.
  • Added a paragraph about ports to the Using Designer Assistance for the Subsystem section in Chapter 4, Design Flow Steps.
10/04/2017 Version 7.1
N/A
  • Added clarification of register availability depending on AXI Ethernet Buffer enabling. See the Note for Table 2-27.
  • Added information about signals generated from *_clocks_resets module in the Include Shared Logic in IP Example Design configuration in Chapter 4, Design Flow Steps.
  • Added a caution after Figure 4-10 about RXOUTCLKs.
06/07/2017 Version 7.1
N/A
  • Updated screen displays in Chapter 4.
  • Updated description of phy_rst_n.in Table 2-14.
  • Added gt_powergood. See Changes from v7.0 to v7.1 in Appendix B.
  • Replaced Table B-1 with sections describing port changes for versions.
04/05/2017 Version 7.0
N/A
  • Added Verilog and VHDL source HDL Model to Simulation Model row in IP Facts table.
  • Added text for timestamping support of 1G and 2.5G mode of operation and support for over Select Input/Output (I/O) Low Voltage Differential Signaling (LVDS) in the Feature Summary in Chapter 1, Overview.
  • Added text about AMD UltraScale™ and AMD UltraScale+™ to the SGMII over LVDS section in Chapter 2.
  • Added text about ports and SGMII in asynchronous and synchronous mode in the 1000BASE-X over LVDS section in Chapter 2.
  • Changed “promiscuous address mode” to “promiscuous mode” throughout.
  • Updated some text in Figure 2-20. Updated AXI4-Lite registers from 0x500-0x78c in Table 2-27.
  • Removed all register descriptions from the Identification register through Address Filter Mask register. Replaced with references to PG051. Also many of the register names were changed.
  • Updated Reset Values in Table 2-43 and 2-44.
  • Added Example 3 section to Chapter 4.
  • Added several paragraphs to the Simulation section in Chapter 4.
10/05/2016 Version 7.0
N/A
  • Added information about the Location tabs in Chapter 4, Design Flow Steps.
  • Added SGMII and 1000BASEX over LVDS support for UltraScale and UltraScale+ devices.
  • Added support for 1588 in SGMII mode.
  • Added Spartan-7 device support.
06/08/2016 Version 7.0
N/A Added support for GT in example design for UltraScale and UltraScale+ devices.
04/06/2016 Version 7.0
N/A Added clock frequency rates for UltraScale devices in User Parameters.
11/18/2015 Version 7.0
N/A Added support for UltraScale+ families.
09/30/2015 Version 7.0
N/A Added SGMII over LVDS support on UltraScale devices.
06/24/2015 Version 7.0
N/A Updated the Received Timestamp Ports (Out of Band) and Received Frame Timestamp In-line with Frame Reception sections in Appendix-A: IEEE 1588 Timestamping.
04/01/2015 Version 7.0
N/A Added support for 2.5G Ethernet on 7 series devices with GTH and GTX transceivers and UltraScale transceivers.
10/01/2014 Version 6.2
N/A
  • Numerous changes to support subsystem nomenclature
  • Added Example Design and Test Bench chapters
04/02/2014 Version 6.1
N/A
  • Added Correction Field update in 1588 functionality.
  • Updated Figure 4-5.
10/02/2013 Version 6.0
N/A
  • Added the Board tab to the Vivado IDE.
  • Updated the screen captures in Chapter 4.
  • Updated the Migrating and Upgrading appendix.
  • Added Shared Logic and Designer Assistance information throughout.
  • Modified Figure 2-1.
  • Added I/O Interfaces table to Chapter 2.
  • Added design parameters table to Chapter 3.
  • Updated most of the information in Chapter 4, Customizing and Generating the Core. Updated all screen captures.
06/19/2013 Version 5.0
N/A
  • Revision number advanced to 5.0 to align with core version number 5.0.
  • Added optional 1588 functionality.
  • Added support for SGMII over LVDS.
03/20/2013 Version 1.0
N/A Initial release.