The Interrupt Enable (IE) register is shown in the following figure. This register, combined with the IS, IP, MIS, and MIE registers, defines the interrupt interface of the subsystem. The Interrupt Enable register uses one bit to represent each subsystem internal interruptible condition represented in the Interrupt Status register. Each bit set in the Interrupt Enable register allows an interruptible condition bit in the Interrupt Status register to pass through to the Interrupt Pending register.
The following table shows the Interrupt Enable register bit definitions.
| Bits | Name | Access | Reset Value | Description |
|---|---|---|---|---|
| 31:9 | Reserved | RO | 0x0 | Reserved: These bits are reserved for future definition and always return zero. |
| 8 | PhyRstCmplt | R/W | 0 |
PHY Reset Complete: Bit used to
enable interrupt.
|
| 7 | MgtRdy | R/W | 0 | MGT Ready: Bit used to enable interrupt.
|
| 6 | RxDcmLock | R/W | 0 |
Receive DCM Lock: Bit used to
enable interrupt.
|
| 5 | TxCmplt | R/W | 0 |
Transmit Complete: Bit used to
enable interrupt.
|
| 4 | RxMemOvr | R/W | 0 |
Receive Memory Overrun: Bit used
to enable interrupt.
|
| 3 | RxRject | R/W | 0 |
Receive Frame Rejected: Bit used
to enable interrupt.
|
| 2 | RxCmplt | R/W | 0 |
Receive Complete:Bit used to
enable interrupt.
|
| 1 | AutoNeg | R/W | 0 |
Auto-Negotiation Complete: Bit
used to enable interrupt.
|
| 0 | HardAcsCmplt | R/W | 0 |
Hard Register Access Complete:
Bit used to enable interrupt.
|