BIST Mode - BIST Mode - 8.0 English - PG138

In BIST mode, the demonstration test bench performs these steps:

1. Input clock signals are generated.
2. A reset is applied to the example design.
3. The required Ethernet MAC bit rate is selected.
4. The MDIO stimulus/response block responds to a read with all 1s indicating no PHY is present.
5. The pattern generator(s) and checker(s) are enabled.
6. The simulation runs for a fixed duration, allowing a large number of frames to pass.
7. Any detected errors or lack of RX activity are reported as errors.
8. If the AVB endpoint is included, the bandwidth of the two data streams is reported.