User STRB/TKEEP Set 1 to 4 - 3.0 English

AXI Traffic Generator LogiCORE IP Product Guide (PG125)

Document ID
PG125
Release Date
2023-10-18
Version
3.0 English

These four registers allow you to set the TSTRB/TKEEP value for the last beat of the transfer. This register along with TLEN allows you to generate transfers with byte level granularity.

Table 1. User STRB/TKEEP Set 1 to 4 (0x40 to 0x4C)
Bits Name Reset Value Access Type Description
31:0 TKTS 0x0 R/W TSTRB/TKEEP value to be appeared on the last beat of the transfer.
  1. For a 32-bit wide TDATA bus to generate a TKEEP/TSTRB value of 0x3, register 0x40 needs to be written with 0x3. 0x44 to 0x4C can be ignored in 32-bit TDATA width case.Because maximum TDATA width supported is 1,024 bits, 128 bits are needed to specify TSTRB/TKEEP values. In such a case, your value of TSTRB/TKEEP needs to be written to 0x40 to 0x4C with least significant bits set in 0x40.