Streaming Control register provides the current version of the AXI4-Stream interface and allows you to enable the core to generate traffic using the programmed configuration. This register is only available in the Streaming mode of operation.
Bits | Name | Reset Value | Access Type | Description |
---|---|---|---|---|
31:24 | Version | 0x20 | R | Version Value |
23:2 | Reserved | N/A | N/A | Reserved |
1 | Done | 0x0 | R/W1C |
Transfer Done 0 = Indicates core is generating traffic when STREN is 1, else core is in idle mode 1 = Indicates traffic generation completed This bit is set to 1 when the core is disabled by setting STREN to 0 and the current transfer is completed. This bit resets to 0 either writing 1 to this bit or enabling the core with STREN. |
0 | STREN | 0x0 | R/W |
Streaming Enable 0 = Disable traffic generation 1 = Enable traffic generation |
|